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authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>2019-12-17 13:10:43 +0300
committerPriyanka Jain <priyanka.jain@nxp.com>2020-01-24 11:58:26 +0300
commit282d992e1a66ecd8e8cca74e0759b7e5b6516e40 (patch)
tree6209071344e4c8a3a98906e96a309b67c96a4677 /drivers/pci
parentf8203e3bb5f99c88199769034fe0f0af2879b96b (diff)
downloadu-boot-282d992e1a66ecd8e8cca74e0759b7e5b6516e40.tar.xz
pci: layerscape: Fix the BARs disable function
There is not any difference for disabling BARs in RC mode between PCIe controllers with and without SRIOV. Fixes: 80afc63fc342 ("pci: layerscape: add pci driver based on DM") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pcie_layerscape.c11
1 files changed, 0 insertions, 11 deletions
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 22d10cf737..2ab67d1fc9 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -312,17 +312,6 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
/* Disable all bars in RC mode */
static void ls_pcie_disable_bars(struct ls_pcie *pcie)
{
- u32 sriov;
-
- sriov = in_le32(pcie->dbi + PCIE_SRIOV);
-
- /*
- * TODO: For PCIe controller with SRIOV, the method to disable bars
- * is different and more complex, so will add later.
- */
- if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
- return;
-
dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
dbi_writel(pcie, 0xfffffffe, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);