Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

- device-tree sync-up with Linux for ls1028a
- fixes/update in fsl-ddr driver, fsl-validate, lx2162a, fsl-mc,
  spintable code, configs, qspi node, pci
- enable EFI_SET_TIME support in sl28
- powerpc: Drop -mstring

5 files changed, 61 insertions, 26 deletions

diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index a58e7a3892..8a2a0e1f4a 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2021 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  */
@@ -24,6 +24,8 @@
 #include "pcie_layerscape.h"
 #include "pcie_layerscape_fixup_common.h"
 
+int next_stream_id;
+
 static int fdt_pcie_get_nodeoffset(void *blob, struct ls_pcie_rc *pcie_rc)
 {
 	int nodeoffset;
@@ -607,6 +609,9 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie_rc *pcie_rc)
 {
 	ft_pcie_ep_fix(blob, pcie_rc);
 	ft_pcie_rc_fix(blob, pcie_rc);
+
+	pcie_rc->stream_id_cur = 0;
+	pcie_rc->next_lut_index = 0;
 }
 
 /* Fixup Kernel DT for PCIe */
@@ -618,6 +623,7 @@ void ft_pci_setup_ls(void *blob, struct bd_info *bd)
 		ft_pcie_ls_setup(blob, pcie_rc);
 
 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
+	next_stream_id = FSL_PEX_STREAM_ID_START;
 	fdt_fixup_pcie_ls(blob);
 #endif
 }
diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c
index 3216a20027..faccf6c141 100644
--- a/drivers/pci/pcie_layerscape_fixup_common.c
+++ b/drivers/pci/pcie_layerscape_fixup_common.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
  *
  * PCIe DT fixup for NXP Layerscape SoCs
  * Author: Wasim Khan <wasim.khan@nxp.com>
@@ -15,6 +15,8 @@
 #include <fdt_support.h>
 #include "pcie_layerscape_fixup_common.h"
 
+extern int next_stream_id;
+
 void ft_pci_setup(void *blob, struct bd_info *bd)
 {
 #if defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
@@ -147,8 +149,6 @@ int pcie_next_streamid(int currentid, int idx)
 /* returns the next available streamid for pcie, -errno if failed */
 int pcie_next_streamid(int currentid, int idx)
 {
-	static int next_stream_id = FSL_PEX_STREAM_ID_START;
-
 	if (next_stream_id > FSL_PEX_STREAM_ID_END)
 		return -EINVAL;
 
diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c
index 255e73181d..6ecdd6af40 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
  *
  * PCIe Gen4 driver for NXP Layerscape SoCs
  * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
@@ -305,8 +305,6 @@ static void ls_pcie_g4_setup_ctrl(struct ls_pcie_g4 *pcie)
 	ccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);
 
 	ls_pcie_g4_setup_wins(pcie);
-
-	pcie->stream_id_cur = 0;
 }
 
 static void ls_pcie_g4_ep_inbound_win_set(struct ls_pcie_g4 *pcie, int pf,
diff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c b/drivers/pci/pcie_layerscape_gen4_fixup.c
index e9ee15558e..7d11234106 100644
--- a/drivers/pci/pcie_layerscape_gen4_fixup.c
+++ b/drivers/pci/pcie_layerscape_gen4_fixup.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
  *
  * PCIe Gen4 driver for NXP Layerscape SoCs
  * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
@@ -223,6 +223,9 @@ static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie)
 {
 	ft_pcie_rc_layerscape_gen4_fix(blob, pcie);
 	ft_pcie_ep_layerscape_gen4_fix(blob, pcie);
+
+	pcie->stream_id_cur = 0;
+	pcie->next_lut_index = 0;
 }
 
 /* Fixup Kernel DT for PCIe */
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index f50d6ef653..17969e2f23 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2020 NXP
+ * Copyright 2020,2021 NXP
  * Layerscape PCIe driver
  */
 
@@ -21,6 +21,12 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct ls_pcie_drvdata {
+	u32 lut_offset;
+	u32 ctrl_offset;
+	bool big_endian;
+};
+
 static void ls_pcie_cfg0_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev)
 {
 	struct ls_pcie *pcie = pcie_rc->pcie;
@@ -238,11 +244,11 @@ static void ls_pcie_setup_ctrl(struct ls_pcie_rc *pcie_rc)
 	ls_pcie_dbi_ro_wr_dis(pcie);
 
 	ls_pcie_disable_bars(pcie_rc);
-	pcie_rc->stream_id_cur = 0;
 }
 
 static int ls_pcie_probe(struct udevice *dev)
 {
+	const struct ls_pcie_drvdata *drvdata = (void *)dev_get_driver_data(dev);
 	struct ls_pcie_rc *pcie_rc = dev_get_priv(dev);
 	const void *fdt = gd->fdt_blob;
 	int node = dev_of_offset(dev);
@@ -260,8 +266,12 @@ static int ls_pcie_probe(struct udevice *dev)
 
 	pcie_rc->pcie = pcie;
 
+	/* try resource name of the official binding first */
 	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
-				     "dbi", &pcie_rc->dbi_res);
+				     "regs", &pcie_rc->dbi_res);
+	if (ret)
+		ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+					     "dbi", &pcie_rc->dbi_res);
 	if (ret) {
 		printf("ls-pcie: resource \"dbi\" not found\n");
 		return ret;
@@ -287,21 +297,29 @@ static int ls_pcie_probe(struct udevice *dev)
 	if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
 		return 0;
 
-	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
-				     "lut", &pcie_rc->lut_res);
-	if (!ret)
-		pcie->lut = map_physmem(pcie_rc->lut_res.start,
-					fdt_resource_size(&pcie_rc->lut_res),
-					MAP_NOCACHE);
+	if (drvdata) {
+		pcie->lut = pcie->dbi + drvdata->lut_offset;
+	} else {
+		ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+					     "lut", &pcie_rc->lut_res);
+		if (!ret)
+			pcie->lut = map_physmem(pcie_rc->lut_res.start,
+						fdt_resource_size(&pcie_rc->lut_res),
+						MAP_NOCACHE);
+	}
 
-	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
-				     "ctrl", &pcie_rc->ctrl_res);
-	if (!ret)
-		pcie->ctrl = map_physmem(pcie_rc->ctrl_res.start,
-					 fdt_resource_size(&pcie_rc->ctrl_res),
-					 MAP_NOCACHE);
-	if (!pcie->ctrl)
-		pcie->ctrl = pcie->lut;
+	if (drvdata) {
+		pcie->ctrl = pcie->lut + drvdata->ctrl_offset;
+	} else {
+		ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+					     "ctrl", &pcie_rc->ctrl_res);
+		if (!ret)
+			pcie->ctrl = map_physmem(pcie_rc->ctrl_res.start,
+						 fdt_resource_size(&pcie_rc->ctrl_res),
+						 MAP_NOCACHE);
+		if (!pcie->ctrl)
+			pcie->ctrl = pcie->lut;
+	}
 
 	if (!pcie->ctrl) {
 		printf("%s: NOT find CTRL\n", dev->name);
@@ -343,7 +361,10 @@ static int ls_pcie_probe(struct udevice *dev)
 	pcie_rc->cfg1 = pcie_rc->cfg0 +
 			fdt_resource_size(&pcie_rc->cfg_res) / 2;
 
-	pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
+	if (drvdata)
+		pcie->big_endian = drvdata->big_endian;
+	else
+		pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
 
 	debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
 	      dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
@@ -373,8 +394,15 @@ static const struct dm_pci_ops ls_pcie_ops = {
 	.write_config	= ls_pcie_write_config,
 };
 
+static const struct ls_pcie_drvdata ls1028a_drvdata = {
+	.lut_offset = 0x80000,
+	.ctrl_offset = 0x40000,
+	.big_endian = false,
+};
+
 static const struct udevice_id ls_pcie_ids[] = {
 	{ .compatible = "fsl,ls-pcie" },
+	{ .compatible = "fsl,ls1028a-pcie", .data = (ulong)&ls1028a_drvdata },
 	{ }
 };