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authorPali Rohár <pali@kernel.org>2021-09-26 01:54:43 +0300
committerStefan Roese <sr@denx.de>2021-10-08 09:37:55 +0300
commit95e101e86ae9d4dbc29ab82bcf1cfa8820a7ba4a (patch)
treee7482e86aebfc9acbd83ff001cf8f40241778673 /drivers/pci
parentcb056005dc674fb5fce89d2b7bdc37594b180b68 (diff)
downloadu-boot-95e101e86ae9d4dbc29ab82bcf1cfa8820a7ba4a.tar.xz
arm: a37xx: pci: Do not automatically enable bus mastering on PCI Bridge
Now that PCI Bridge is working for the PCIe Root Port, U-Boot's PCI_PNP code automatically enables memory access and bus mastering when needed. We do not need to enable it when setting the HW up. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pci-aardvark.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 082fdc3b74..2481cbea52 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -910,12 +910,6 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
if (pcie_advk_wait_for_link(pcie))
return -ENXIO;
- reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
- reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
- PCIE_CORE_CMD_IO_ACCESS_EN |
- PCIE_CORE_CMD_MEM_IO_REQ_EN;
- advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
-
return 0;
}