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| author | Tom Rini <trini@konsulko.com> | 2017-01-26 01:09:01 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-01-26 01:38:45 +0300 |
| commit | 79a34b71c943a80af5c6d9a2af736fbb37dcc14c (patch) | |
| tree | c903d3136106e2a566c33eb1366f110220f4c366 /drivers/pci | |
| parent | a8523a808fd05e4b1c1df63bc40744dd3fd318f4 (diff) | |
| parent | 76866600f544f00928ee9b5b2799a091ea9b80a7 (diff) | |
| download | u-boot-79a34b71c943a80af5c6d9a2af736fbb37dcc14c.tar.xz | |
Merge git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/fsl_pci_init.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 52792dcd59..af20cf0f3e 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -543,6 +543,13 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); } +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815 + /* The Read-Only Write Enable bit defaults to 1 instead of 0. + * Set to 0 to protect the read-only registers. + */ + clrbits_be32(&pci->dbi_ro_wr_en, 0x01); +#endif + /* Use generic setup_device to initialize standard pci regs, * but do not allocate any windows since any BAR found (such * as PCSRBAR) is not in this cpu's memory space. |