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authorPali Rohár <pali@kernel.org>2021-09-24 17:11:57 +0300
committerStefan Roese <sr@denx.de>2021-10-08 09:33:52 +0300
commit021a98a2d6512bf59581675a997d659b18c09306 (patch)
treeca6dda07a319a15771a5ab024ea3e7b1c4f10854 /drivers/phy
parent4ca474d3067ba7278c6a5f94ff4340ca5a07ca0a (diff)
downloadu-boot-021a98a2d6512bf59581675a997d659b18c09306.tar.xz
phy: marvell: a3700: Return correct error code when power up fails
Subroutines in comphy_usb2_power_up() and comphy_sgmii_power_up() functions may fail. In this case, do not continue execution of current function and instead jump to the end. Return value in 'ret' variable is already set. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/phy')
-rw-r--r--drivers/phy/marvell/comphy_a3700.c26
1 files changed, 20 insertions, 6 deletions
diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
index 69cd63edb1..047c8bb045 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -594,24 +594,30 @@ static int comphy_usb2_power_up(u8 usb32)
rb_usb2phy_pllcal_done, /* value */
rb_usb2phy_pllcal_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to end USB2 PLL calibration\n");
+ goto out;
+ }
/* Assert impedance calibration done */
ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32),
rb_usb2phy_impcal_done, /* value */
rb_usb2phy_impcal_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to end USB2 impedance calibration\n");
+ goto out;
+ }
/* Assert squetch calibration done */
ret = comphy_poll_reg(USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32),
rb_usb2phy_sqcal_done, /* value */
rb_usb2phy_sqcal_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to end USB2 unknown calibration\n");
+ goto out;
+ }
/* Assert PLL is ready */
ret = comphy_poll_reg(USB2_PHY_PLL_CTRL0_ADDR(usb32),
@@ -619,9 +625,12 @@ static int comphy_usb2_power_up(u8 usb32)
rb_usb2phy_pll_ready, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to lock USB2 PLL\n");
+ goto out;
+ }
+out:
debug_exit();
return ret;
@@ -873,8 +882,10 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
rb_pll_ready_tx | rb_pll_ready_rx, /* value */
rb_pll_ready_tx | rb_pll_ready_rx, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to lock PLL for SGMII PHY %d\n", lane);
+ goto out;
+ }
/*
* 21. Set COMPHY input port PIN_TX_IDLE=0
@@ -895,14 +906,17 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
rb_rx_init_done, /* value */
rb_rx_init_done, /* mask */
POLL_32B_REG); /* 32bit */
- if (!ret)
+ if (!ret) {
printf("Failed to init RX of SGMII PHY %d\n", lane);
+ goto out;
+ }
/*
* Restore saved selector.
*/
reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF);
+out:
debug_exit();
return ret;