diff options
| author | Igal Liberman <igall@marvell.com> | 2017-04-30 20:16:55 +0300 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2021-04-29 08:45:24 +0300 |
| commit | 3e69b4abffdd2b11b9d382e3a21414d6b7640efe (patch) | |
| tree | 1974e47b1ec582ce186117444366fc2da8767af2 /drivers/phy | |
| parent | 22bc868e4919684f83eb2959ea1163cb06877ddf (diff) | |
| download | u-boot-3e69b4abffdd2b11b9d382e3a21414d6b7640efe.tar.xz | |
phy: marvell: cp110: utmi: update analog parameters according to latest ETP
Add UTMI analog parameters initialization values according to
latest ETP.
Change-Id: I5bcca205a3995202a18ff126f371a81f69e205c8
Signed-off-by: Igal Liberman <igall@marvell.com>
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/marvell/comphy_cp110.c | 9 | ||||
| -rw-r--r-- | drivers/phy/marvell/utmi_phy.h | 5 |
2 files changed, 7 insertions, 7 deletions
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 82d8693688..72563f8bc1 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -614,15 +614,12 @@ static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr, /* Impedance Calibration Threshold Setting */ reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG, - 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, + 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); /* Set LS TX driver strength coarse control */ - mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; - data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; - /* Set LS TX driver fine adjustment */ - mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; - data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; + mask = UTMI_TX_CH_CTRL_AMP_MASK; + data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET; reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask); /* Enable SQ */ diff --git a/drivers/phy/marvell/utmi_phy.h b/drivers/phy/marvell/utmi_phy.h index 682a3acc40..fa6bf3c914 100644 --- a/drivers/phy/marvell/utmi_phy.h +++ b/drivers/phy/marvell/utmi_phy.h @@ -52,6 +52,9 @@ #define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16 #define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK \ (0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET) +#define UTMI_TX_CH_CTRL_AMP_OFFSET 20 +#define UTMI_TX_CH_CTRL_AMP_MASK \ + (0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET) #define UTMI_RX_CH_CTRL0_REG 0x14 #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15 @@ -64,7 +67,7 @@ #define UTMI_RX_CH_CTRL1_REG 0x18 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK \ - (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) + (0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK \ (0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET) |