diff options
| author | Jagan Teki <jagan@amarulasolutions.com> | 2019-07-16 14:57:01 +0300 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-07-20 18:59:44 +0300 |
| commit | 01cc1039153d0ca4202e8b944e321637e27adc86 (patch) | |
| tree | 02ae2d608cb709610b26a1e605285273c8d27cb3 /drivers/ram/rockchip | |
| parent | e0ddb0ba214f0bf05a66094a347169e617936c2b (diff) | |
| download | u-boot-01cc1039153d0ca4202e8b944e321637e27adc86.tar.xz | |
ram: rk3399: Introduce sys_reg3 for more capacity info
cs0_row, cs1_row and cs1_col needs more bits to show its
correct value, update to make use of both sys_reg2,
sys_reg3.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
(Squash similar patches into one patch)
Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/ram/rockchip')
| -rw-r--r-- | drivers/ram/rockchip/sdram_rk3399.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 38ae6d174a..fed9f94840 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1074,6 +1074,7 @@ static void dram_all_config(struct dram_info *dram, const struct rk3399_sdram_params *params) { u32 sys_reg2 = 0; + u32 sys_reg3 = 0; unsigned int channel, idx; sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype); @@ -1094,10 +1095,13 @@ static void dram_all_config(struct dram_info *dram, sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel); sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel); sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel); - sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel); - sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel); sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel); sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel); + SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel); + if (info->cap_info.cs1_row) + SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2, + sys_reg3, channel); + sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel); ddr_msch_regs = dram->chan[channel].msch; noc_timing = ¶ms->ch[channel].noc_timings; @@ -1119,6 +1123,7 @@ static void dram_all_config(struct dram_info *dram, } writel(sys_reg2, &dram->pmugrf->os_reg2); + writel(sys_reg3, &dram->pmugrf->os_reg3); rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, params->base.stride << 10); |