diff options
| author | Jagan Teki <jagan@edgeble.ai> | 2022-12-14 20:50:50 +0300 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2023-01-16 13:01:10 +0300 |
| commit | 5ab30c3176bfda282d8e350c41d9731214eac582 (patch) | |
| tree | 6b60b4d6d81ea36fec5c73fee6aa9dea80770104 /drivers/ram/rockchip | |
| parent | 29c31489743a92d8be9446afa778dde0ba702111 (diff) | |
| download | u-boot-5ab30c3176bfda282d8e350c41d9731214eac582.tar.xz | |
ram: rockchip: Update ddr pctl regs for px30
Add full ddr pctl registers and bit masks for px30.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/ram/rockchip')
| -rw-r--r-- | drivers/ram/rockchip/sdram_pctl_px30.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/ram/rockchip/sdram_pctl_px30.c b/drivers/ram/rockchip/sdram_pctl_px30.c index 331d85fba2..e5c80fb83b 100644 --- a/drivers/ram/rockchip/sdram_pctl_px30.c +++ b/drivers/ram/rockchip/sdram_pctl_px30.c @@ -21,7 +21,7 @@ void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num) setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31); while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31)) continue; - while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY) + while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY) continue; } @@ -33,7 +33,7 @@ void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num) int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg, u32 dramtype) { - while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY) + while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY) continue; if (dramtype == DDR3 || dramtype == DDR4) { writel((mr_num << 12) | (rank << 4) | (0 << 0), @@ -49,7 +49,7 @@ int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg, setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31); while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31)) continue; - while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY) + while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY) continue; return 0; |