diff options
author | Samin Guo <samin.guo@starfivetech.com> | 2023-06-14 06:00:03 +0300 |
---|---|---|
committer | Samin Guo <samin.guo@starfivetech.com> | 2023-07-10 06:43:53 +0300 |
commit | 0f9fbb815e29bac141c2d15a85f393765d497093 (patch) | |
tree | 808d851b634b8304f2df3fe6b40a839f50c58c62 /drivers/ram/starfive | |
parent | be8d0d0730b1023f0877ec01bf2d0763b0214ba4 (diff) | |
download | u-boot-0f9fbb815e29bac141c2d15a85f393765d497093.tar.xz |
dram: starfive: jh7110: Add 1G support
add 1G DDR tuning cfg
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Diffstat (limited to 'drivers/ram/starfive')
-rw-r--r-- | drivers/ram/starfive/ddrcsr_boot.c | 38 | ||||
-rw-r--r-- | drivers/ram/starfive/ddrphy_start.c | 22 | ||||
-rw-r--r-- | drivers/ram/starfive/starfive_ddr.c | 5 | ||||
-rw-r--r-- | drivers/ram/starfive/starfive_ddr.h | 10 |
4 files changed, 46 insertions, 29 deletions
diff --git a/drivers/ram/starfive/ddrcsr_boot.c b/drivers/ram/starfive/ddrcsr_boot.c index 048b838b3d..469e280938 100644 --- a/drivers/ram/starfive/ddrcsr_boot.c +++ b/drivers/ram/starfive/ddrcsr_boot.c @@ -15,13 +15,15 @@ static struct ddr_reg_cfg ddr_csr_cfg[] = { {0x0, 0x0, 0x00000001, REGSETALL}, {0xf00, 0x0, 0x40001030, (OFFSET_SEL | F_SET | REG4G | REG8G)}, - {0xf00, 0x0, 0x40001030, (OFFSET_SEL | F_SET | REG2G)}, + {0xf00, 0x0, 0x40001010, (OFFSET_SEL | F_SET | REG2G)}, + {0xf00, 0x0, 0x40001010, (OFFSET_SEL | F_SET | REG1G)}, {0xf04, 0x0, 0x00000001, (OFFSET_SEL | F_SET | REG4G | REG8G)}, - {0xf04, 0x0, 0x00800001, (OFFSET_SEL | F_SET | REG2G)}, + {0xf04, 0x0, 0x00800001, (OFFSET_SEL | F_SET | REG1G | REG2G)}, {0xf10, 0x0, 0x00400000, (OFFSET_SEL | REGSETALL)}, {0xf14, 0x0, 0x043fffff, (OFFSET_SEL | REGSETALL)}, {0xf18, 0x0, 0x00000000, (OFFSET_SEL | REGSETALL)}, - {0xf30, 0x0, 0x1f000041, (OFFSET_SEL | REGSETALL)}, + {0xf30, 0x0, 0x1f000041, (OFFSET_SEL | F_SET | REG2G | REG4G | REG8G)}, + {0xf30, 0x0, 0x07000021, (OFFSET_SEL | F_SET | REG1G)}, {0xf34, 0x0, 0x1f000041, (OFFSET_SEL | F_SET | REG4G | REG8G)}, {0x110, 0x0, 0xc0000001, (OFFSET_SEL | REGSETALL)}, {0x114, 0x0, 0xffffffff, (OFFSET_SEL | REGSETALL)}, @@ -74,19 +76,19 @@ static struct ddr_reg_cfg ddr_csr_cfg1[] = { {0x6a4, 0x0, 0x20240c00, REGSETALL}, {0x6a8, 0x0, 0x00040000, REGSETALL}, {0x4, 0x0, 0x30010006, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x10010006, (F_SET | REG2G)}, + {0x4, 0x0, 0x10010006, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x4, 0x0, 0x30020000, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x10020000, (F_SET | REG2G)}, + {0x4, 0x0, 0x10020000, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x4, 0x0, 0x30030031, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x10030031, (F_SET | REG2G)}, + {0x4, 0x0, 0x10030031, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x4, 0x0, 0x300b0033, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x100b0033, (F_SET | REG2G)}, + {0x4, 0x0, 0x100b0033, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x4, 0x0, 0x30160016, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x10160016, (F_SET | REG2G)}, + {0x4, 0x0, 0x10160016, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x10, 0x0, 0x00000010, REGSETALL}, {0x14, 0x0, 0x00000001, REGSETALL}, @@ -153,20 +155,20 @@ static struct ddr_reg_cfg ddr_csr_cfg3[] = { {0x6a4, 0x0, 0x202c0c00, REGSETALL}, {0x6a8, 0x0, 0x00040000, REGSETALL}, {0x4, 0x0, 0x30010036, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x10010036, (F_SET | REG2G)}, + {0x4, 0x0, 0x10010036, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x4, 0x0, 0x3002001b, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x10010036, (F_SET | REG2G)}, + {0x4, 0x0, 0x1002001b, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x4, 0x0, 0x30030031, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x10030031, (F_SET | REG2G)}, + {0x4, 0x0, 0x10030031, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x4, 0x0, 0x300b0066, (F_SET | REG4G)}, {0x4, 0x0, 0x300b0036, (F_SET | REG8G)}, - {0x4, 0x0, 0x100b0066, (F_SET | REG2G)}, + {0x4, 0x0, 0x100b0066, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x4, 0x0, 0x30160016, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x10160016, (F_SET | REG2G)}, + {0x4, 0x0, 0x10160016, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x410, 0x0, 0x00101010, REGSETALL}, {0x420, 0x0, 0x0c181006, REGSETALL}, @@ -176,9 +178,9 @@ static struct ddr_reg_cfg ddr_csr_cfg3[] = { {0x108, 0x0, 0x00003000, REGSETALL}, {0x704, 0x0, 0x00000007, REGSETALL | OFFSET_SEL}, {0x330, 0x0, 0x09313fff, (F_SET | REG4G | REG8G)}, - {0x330, 0x0, 0x09311fff, (F_SET | REG2G)}, + {0x330, 0x0, 0x09311fff, (F_SET | REG1G | REG2G)}, {0x508, 0x0, 0x00000033, (F_SET | REG4G | REG8G)}, - {0x508, 0x0, 0x00000013, (F_SET | REG2G)}, + {0x508, 0x0, 0x00000013, (F_SET | REG1G | REG2G)}, {0x324, 0x0, 0x00002000, REGSETALL}, {0x104, 0x0, 0x90000000, REGSETALL}, {0x510, 0x0, 0x00000100, REGSETALL}, @@ -217,6 +219,10 @@ void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size) u32 mask; switch (size) { + case DDR_SIZE_1G: + mask = REG1G; + break; + case DDR_SIZE_2G: mask = REG2G; break; @@ -249,6 +255,7 @@ void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size) udelay(3000); switch (size) { + case DDR_SIZE_1G: case DDR_SIZE_2G: out_le32(csrreg + REGOFFSET(0x10), 0x0000001c); break; @@ -279,6 +286,7 @@ void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size) out_le32(csrreg + REGOFFSET(0x10), 0x00000021); out_le32(csrreg + REGOFFSET(0x14), 0x00000001); break; + case DDR_SIZE_1G: case DDR_SIZE_2G: case DDR_SIZE_16G: default: diff --git a/drivers/ram/starfive/ddrphy_start.c b/drivers/ram/starfive/ddrphy_start.c index 58165e427c..3ec587276d 100644 --- a/drivers/ram/starfive/ddrphy_start.c +++ b/drivers/ram/starfive/ddrphy_start.c @@ -79,7 +79,7 @@ static struct ddr_reg_cfg ddr_start_cfg[] = { {185, 0x80ffffff, 0x20000000, REGCLRSETALL}, {10, 0xffffffe0, 0x00000002, REGCLRSETALL}, {0, 0xfffffffe, 0x00000001, REGCLRSETALL}, - {11, 0xfffffff0, 0x00000005, (F_CLRSET | REG2G)}, + {11, 0xfffffff0, 0x00000005, (F_CLRSET | REG1G | REG2G)}, {247, 0xffffffff, 0x00000008, REGCLRSETALL}, {249, 0xffffffff, 0x00000800, REGCLRSETALL}, {252, 0xffffffff, 0x00000008, REGCLRSETALL}, @@ -92,10 +92,10 @@ static struct ddr_reg_cfg ddr_start_cfg[] = { {313, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, {337, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, {361, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, - {289, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, - {313, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, - {337, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, - {361, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, + {289, 0xffffffff, 0x66000000, (F_CLRSET | REG1G | REG2G | REG4G)}, + {313, 0xffffffff, 0x66000000, (F_CLRSET | REG1G | REG2G | REG4G)}, + {337, 0xffffffff, 0x66000000, (F_CLRSET | REG1G | REG2G | REG4G)}, + {361, 0xffffffff, 0x66000000, (F_CLRSET | REG1G | REG2G | REG4G)}, {282, 0xffffffff, 0x00160000, REGCLRSETALL}, {306, 0xffffffff, 0x00160000, REGCLRSETALL}, {330, 0xffffffff, 0x00160000, REGCLRSETALL}, @@ -162,7 +162,7 @@ static struct ddr_reg_cfg ddr_start_cfg[] = { {1915, 0x0, 0xc3c37ff, (OFFSET_SEL | REGSETALL)}, {1916, 0x0, 0x1fffff10, (OFFSET_SEL | REGSETALL)}, {1917, 0x0, 0x230070, (OFFSET_SEL | REGSETALL)}, - {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG4G | REG2G | F_SET)}, + {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG4G | REG1G | REG2G | F_SET)}, {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG8G | F_SET)}, {1919, 0x0, 0xe10, (OFFSET_SEL | REGSETALL)}, {1920, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)}, @@ -186,9 +186,9 @@ static struct ddr_reg_cfg ddr_start_cfg[] = { {333, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)}, {589, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)}, {845, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)}, - {1062, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)}, - {1318, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)}, - {1574, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)}, + {1062, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG1G | REG2G | F_CLRSET)}, + {1318, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG1G | REG2G | F_CLRSET)}, + {1574, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG1G | REG2G | F_CLRSET)}, {1062, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)}, {1318, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)}, {1574, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)}, @@ -256,6 +256,10 @@ void ddr_phy_start(u32 *phyreg, enum ddr_size_t size) u32 mask; switch (size) { + case DDR_SIZE_1G: + mask = REG1G; + break; + case DDR_SIZE_2G: mask = REG2G; break; diff --git a/drivers/ram/starfive/starfive_ddr.c b/drivers/ram/starfive/starfive_ddr.c index 0ce2e54652..049b83d129 100644 --- a/drivers/ram/starfive/starfive_ddr.c +++ b/drivers/ram/starfive/starfive_ddr.c @@ -38,6 +38,9 @@ static int starfive_ddr_setup(struct udevice *dev, struct starfive_ddr_priv *pri enum ddr_size_t size; switch (priv->info.size) { + case 0x40000000: + size = DDR_SIZE_1G; + break; case 0x80000000: size = DDR_SIZE_2G; break; @@ -121,7 +124,7 @@ static int starfive_ddr_probe(struct udevice *dev) reset_deassert(&priv->rst_axi); ret = starfive_ddr_setup(dev, priv); - printf("DDR version: dc2e84f0.\n"); + printf("DDR: %ldG version: g8ad50857.\n", priv->info.size/1024/1024/1024); goto init_end; err_osc: reset_free(&priv->rst_osc); diff --git a/drivers/ram/starfive/starfive_ddr.h b/drivers/ram/starfive/starfive_ddr.h index d63e7e4c83..aa7ee988e4 100644 --- a/drivers/ram/starfive/starfive_ddr.h +++ b/drivers/ram/starfive/starfive_ddr.h @@ -27,13 +27,14 @@ #define DDR_AXI_ENABLE 1 #define OFFSET_SEL BIT(31) -#define REG2G BIT(30) -#define REG4G BIT(29) -#define REG8G BIT(28) +#define REG1G BIT(30) +#define REG2G BIT(29) +#define REG4G BIT(28) +#define REG8G BIT(27) #define F_ADDSET BIT(2) #define F_SET BIT(1) #define F_CLRSET BIT(0) -#define REGALL (REG2G | REG4G | REG8G) +#define REGALL (REG1G | REG2G | REG4G | REG8G) #define REGSETALL (F_SET | REGALL) #define REGCLRSETALL (F_CLRSET | REGALL) #define REGADDSETALL (F_ADDSET | REGALL) @@ -46,6 +47,7 @@ struct ddr_reg_cfg { }; enum ddr_size_t { + DDR_SIZE_1G, DDR_SIZE_2G, DDR_SIZE_4G, DDR_SIZE_8G, |