diff options
| author | Jagan Teki <jagan@amarulasolutions.com> | 2019-07-16 14:57:19 +0300 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-07-20 18:59:44 +0300 |
| commit | 66912baa0f00b915df5d2135c40e62b58c965669 (patch) | |
| tree | 3912c59b15c70ef61fa813219ff083aa52d4d370 /drivers/ram | |
| parent | 4e9de9eba844a2432a40ffb4ce7a07f9d786e940 (diff) | |
| download | u-boot-66912baa0f00b915df5d2135c40e62b58c965669.tar.xz | |
ram: rk3399: Configure tsel write ca for lpddr4
tsel write ca_p and ca_n values need to write on PHY 544, 672
and 800 to configure ds odt.
Configure the same PHY register for lpddr4 would require a mask
value of (300 << 8).
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/ram')
| -rw-r--r-- | drivers/ram/rockchip/sdram_rk3399.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 2498620aec..3e069ab0ef 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -502,9 +502,18 @@ static void set_ds_odt(const struct chan_info *chan, /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4); - clrsetbits_le32(&denali_phy[544], 0xff, reg_value); - clrsetbits_le32(&denali_phy[672], 0xff, reg_value); - clrsetbits_le32(&denali_phy[800], 0xff, reg_value); + if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) { + /* LPDDR4 these register read always return 0, so + * can not use clrsetbits_le32(), need to write32 + */ + writel((0x300 << 8) | reg_value, &denali_phy[544]); + writel((0x300 << 8) | reg_value, &denali_phy[672]); + writel((0x300 << 8) | reg_value, &denali_phy[800]); + } else { + clrsetbits_le32(&denali_phy[544], 0xff, reg_value); + clrsetbits_le32(&denali_phy[672], 0xff, reg_value); + clrsetbits_le32(&denali_phy[800], 0xff, reg_value); + } /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ clrsetbits_le32(&denali_phy[928], 0xff, reg_value); |