ram: starfive: Make DDR driver support 8G size

This patch include four  items:
    1.rename the driver compatible name.
    2.reset action with the common API.
    3.clean up code to make it is closer to readable.
    4.add configuration to support 8G size

Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>

4 files changed, 547 insertions, 733 deletions

diff --git a/drivers/ram/starfive/ddrcsr_boot.c b/drivers/ram/starfive/ddrcsr_boot.c
index f8d8eb5451..eff862a175 100644
--- a/drivers/ram/starfive/ddrcsr_boot.c
+++ b/drivers/ram/starfive/ddrcsr_boot.c
@@ -4,332 +4,238 @@
  * Author:	yanhong <yanhong.wang@starfivetech.com>
  *
  */
+#include <common.h>
+#include <asm/io.h>
 
 #include "starfive_ddr.h"
 #include <linux/delay.h>
 
-#define DDRSEC_SEL	0x80000000
 #define REGOFFSET(offset)	((offset) / 4)
 
-static struct ddr_reg_set ddr_cfg[] = {
-	{0x0,			0x00000001},
-	{(DDRSEC_SEL | 0xf00),	0x40001030},
-	{(DDRSEC_SEL | 0xf04),	0x00000001},
-	{(DDRSEC_SEL | 0xf10),	0x00400000},
-	{(DDRSEC_SEL | 0xf14),	0x043fffff},
-	{(DDRSEC_SEL | 0xf18),	0x00000000},
-	{(DDRSEC_SEL | 0xf30),	0x1f000041},
-	{(DDRSEC_SEL | 0xf34),	0x1f000041},
-	{(DDRSEC_SEL | 0x110),	0xc0000001},
-	{(DDRSEC_SEL | 0x114),	0xffffffff},
-	{0x10c,			0x00000505},
-	{0x11c,			0x00000000},
-	{0x500,			0x00000201},
-	{0x514,			0x00000100},
-	{0x6a8,			0x00040000},
-	{0xea8,			0x00040000},
-	{0x504,			0x40000000}
+static struct ddr_reg_cfg ddr_csr_cfg[] = {
+	{0x0,		0x0,	0x00000001,	REGSETALL},
+	{0xf00,		0x0,	0x40001030,	(OFFSET_SEL | F_SET | REG4G | REG8G)},
+	{0xf00,		0x0,	0x40001030,	(OFFSET_SEL | F_SET | REG2G)},
+	{0xf04,		0x0,	0x00000001,	(OFFSET_SEL | F_SET | REG4G | REG8G)},
+	{0xf04,		0x0,	0x00800001,	(OFFSET_SEL | F_SET | REG2G)},
+	{0xf10,		0x0,	0x00400000,	(OFFSET_SEL | REGSETALL)},
+	{0xf14,		0x0,	0x043fffff,	(OFFSET_SEL | REGSETALL)},
+	{0xf18,		0x0,	0x00000000,	(OFFSET_SEL | REGSETALL)},
+	{0xf30,		0x0,	0x1f000041,	(OFFSET_SEL | REGSETALL)},
+	{0xf34,		0x0,	0x1f000041,	(OFFSET_SEL | F_SET | REG4G | REG8G)},
+	{0x110,		0x0,	0xc0000001,	(OFFSET_SEL | REGSETALL)},
+	{0x114,		0x0,	0xffffffff,	(OFFSET_SEL | REGSETALL)},
+	{0x10c,		0x0,	0x00000505,	REGSETALL},
+	{0x11c,		0x0,	0x00000000,	REGSETALL},
+	{0x500,		0x0,	0x00000201,	REGSETALL},
+	{0x514,		0x0,	0x00000100,	REGSETALL},
+	{0x6a8,		0x0,	0x00040000,	REGSETALL},
+	{0xea8,		0x0,	0x00040000,	REGSETALL},
+	{0x504,		0x0,	0x40000000,	REGSETALL}
 };
 
-static struct ddr_reg_set ddr_cfg_2g[] = {
-	{0x0,			0x00000001},
-	{(DDRSEC_SEL | 0xf00),	0x40001010},
-	{(DDRSEC_SEL | 0xf04),	0x00800001},
-	{(DDRSEC_SEL | 0xf10),	0x00400000},
-	{(DDRSEC_SEL | 0xf14),	0x043fffff},
-	{(DDRSEC_SEL | 0xf18),	0x00000000},
-	{(DDRSEC_SEL | 0xf30),	0x1f000041},
-	{(DDRSEC_SEL | 0x110),	0xc0000001},
-	{(DDRSEC_SEL | 0x114),	0xffffffff},
-	{0x10c,			0x00000505},
-	{0x11c,			0x00000000},
-	{0x500,			0x00000201},
-	{0x514,			0x00000100},
-	{0x6a8,			0x00040000},
-	{0xea8,			0x00040000},
-	{0x504,			0x40000000}
+static struct ddr_reg_cfg ddr_csr_cfg1[] = {
+	{0x310,		0x0,	0x00020000,	REGSETALL},
+	{0x310,		0x0,	0x00020001,	REGSETALL},
+	{0x600,		0x0,	0x002e0176,	REGSETALL},
+	{0x604,		0x0,	0x002e0176,	REGSETALL},
+	{0x608,		0x0,	0x001700bb,	REGSETALL},
+	{0x60c,		0x0,	0x000b005d,	REGSETALL},
+	{0x610,		0x0,	0x0005002e,	REGSETALL},
+	{0x614,		0x0,	0x00020017,	REGSETALL},
+	{0x618,		0x0,	0x00020017,	REGSETALL},
+	{0x61c,		0x0,	0x00020017,	REGSETALL},
+	{0x678,		0x0,	0x00000019,	REGSETALL},
+	{0x100,		0x0,	0x000000f8,	REGSETALL},
+	{0x620,		0x0,	0x03030404,	REGSETALL},
+	{0x624,		0x0,	0x04030505,	REGSETALL},
+	{0x628,		0x0,	0x07030884,	REGSETALL},
+	{0x62c,		0x0,	0x13150401,	REGSETALL},
+	{0x630,		0x0,	0x17150604,	REGSETALL},
+	{0x634,		0x0,	0x00110000,	REGSETALL},
+	{0x638,		0x0,	0x200a0a08,	REGSETALL},
+	{0x63c,		0x0,	0x1730f803,	REGSETALL},
+	{0x640,		0x0,	0x000a0c00,	REGSETALL},
+	{0x644,		0x0,	0xa005000a,	REGSETALL},
+	{0x648,		0x0,	0x00000000,	REGSETALL},
+	{0x64c,		0x0,	0x00081306,	REGSETALL},
+	{0x650,		0x0,	0x04070304,	REGSETALL},
+	{0x654,		0x0,	0x00000404,	REGSETALL},
+	{0x658,		0x0,	0x00000060,	REGSETALL},
+	{0x65c,		0x0,	0x00030008,	REGSETALL},
+	{0x660,		0x0,	0x00000000,	REGSETALL},
+	{0x680,		0x0,	0x00000603,	REGSETALL},
+	{0x684,		0x0,	0x01000202,	REGSETALL},
+	{0x688,		0x0,	0x0413040d,	REGSETALL},
+	{0x68c,		0x0,	0x20002420,	REGSETALL},
+	{0x690,		0x0,	0x00140000,	REGSETALL},
+	{0x69c,		0x0,	0x01240074,	REGSETALL},
+	{0x6a0,		0x0,	0x00000000,	REGSETALL},
+	{0x6a4,		0x0,	0x20240c00,	REGSETALL},
+	{0x6a8,		0x0,	0x00040000,	REGSETALL},
+	{0x4,		0x0,	0x30010006,	(F_SET | REG4G | REG8G)},
+	{0x4,		0x0,	0x10010006,	(F_SET | REG2G)},
+	{0xc,		0x0,	0x00000002,	REGSETALL},
+	{0x4,		0x0,	0x30020000,	(F_SET | REG4G | REG8G)},
+	{0x4,		0x0,	0x10020000,	(F_SET | REG2G)},
+	{0xc,		0x0,	0x00000002,	REGSETALL},
+	{0x4,		0x0,	0x30030031,	(F_SET | REG4G | REG8G)},
+	{0x4,		0x0,	0x10030031,	(F_SET | REG2G)},
+	{0xc,		0x0,	0x00000002,	REGSETALL},
+	{0x4,		0x0,	0x300b0033,	(F_SET | REG4G | REG8G)},
+	{0x4,		0x0,	0x100b0033,	(F_SET | REG2G)},
+	{0xc,		0x0,	0x00000002,	REGSETALL},
+	{0x4,		0x0,	0x30160016,	(F_SET | REG4G | REG8G)},
+	{0x4,		0x0,	0x10160016,	(F_SET | REG2G)},
+	{0xc,		0x0,	0x00000002,	REGSETALL},
+	{0x10,		0x0,	0x00000010,	REGSETALL},
+	{0x14,		0x0,	0x00000001,	REGSETALL},
 };
 
-static struct ddr_reg_set ddr_cfg1[] = {
-	{0x310,		0x00020000},
-	{0x310,		0x00020001},
-	{0x600,		0x002e0176},
-	{0x604,		0x002e0176},
-	{0x608,		0x001700bb},
-	{0x60c,		0x000b005d},
-	{0x610,		0x0005002e},
-	{0x614,		0x00020017},
-	{0x618,		0x00020017},
-	{0x61c,		0x00020017},
-	{0x678,		0x00000019},
-	{0x100,		0x000000f8},
-	{0x620,		0x03030404},
-	{0x624,		0x04030505},
-	{0x628,		0x07030884},
-	{0x62c,		0x13150401},
-	{0x630,		0x17150604},
-	{0x634,		0x00110000},
-	{0x638,		0x200a0a08},
-	{0x63c,		0x1730f803},
-	{0x640,		0x000a0c00},
-	{0x644,		0xa005000a},
-	{0x648,		0x00000000},
-	{0x64c,		0x00081306},
-	{0x650,		0x04070304},
-	{0x654,		0x00000404},
-	{0x658,		0x00000060},
-	{0x65c,		0x00030008},
-	{0x660,		0x00000000},
-	{0x680,		0x00000603},
-	{0x684,		0x01000202},
-	{0x688,		0x0413040d},
-	{0x68c,		0x20002420},
-	{0x690,		0x00140000},
-	{0x69c,		0x01240074},
-	{0x6a0,		0x00000000},
-	{0x6a4,		0x20240c00},
-	{0x6a8,		0x00040000},
-	{0x4,		0x30010006},
-	{0xc,		0x00000002},
-	{0x4,		0x30020000},
-	{0xc,		0x00000002},
-	{0x4,		0x30030031},
-	{0xc,		0x00000002},
-	{0x4,		0x300b0033},
-	{0xc,		0x00000002},
-	{0x4,		0x30160016},
-	{0xc,		0x00000002},
-	{0x10,		0x00000010},
-	{0x14,		0x00000001},
+static struct ddr_reg_cfg ddr_csr_cfg2[] = {
+	{0xb8,		0xf0ffffff,		0x3000000,	REGCLRSETALL},
+	{0x84,		0xFEFFFFFF,		0x0,		REGCLRSETALL},
+	{0xb0,		0xFFFEFFFF,		0x0,		REGCLRSETALL},
+	{0xb0,		0xFEFFFFFF,		0x0,		REGCLRSETALL},
+	{0xb4,		0xffffffff,		0x1,		REGCLRSETALL},
+	{0x248,		0xffffffff,		0x3000000,	REGCLRSETALL},
+	{0x24c,		0xffffffff,		0x300,		REGCLRSETALL},
+	{0x24c,		0xffffffff,		0x3000000,	REGCLRSETALL},
+	{0xb0,		0xffffffff,		0x100,		REGCLRSETALL},
+	{0xb8,		0xFFF0FFFF,		0x30000,	REGCLRSETALL},
+	{0x84,		0xFFFEFFFF,		0x0,		REGCLRSETALL},
+	{0xac,		0xFFFEFFFF,		0x0,		REGCLRSETALL},
+	{0xac,		0xFEFFFFFF,		0x0,		REGCLRSETALL},
+	{0xb0,		0xffffffff,		0x1,		REGCLRSETALL},
+	{0x248,		0xffffffff,		0x30000,	REGCLRSETALL},
+	{0x24c,		0xffffffff,		0x3,		REGCLRSETALL},
+	{0x24c,		0xffffffff,		0x30000,	REGCLRSETALL},
+	{0x250,		0xffffffff,		0x3000000,	REGCLRSETALL},
+	{0x254,		0xffffffff,		0x3000000,	REGCLRSETALL},
+	{0x258,		0xffffffff,		0x3000000,	REGCLRSETALL},
+	{0xac,		0xffffffff,		0x100,		REGCLRSETALL},
+	{0x10c,		0xFFFFF0FF,		0x300,		REGCLRSETALL},
+	{0x110,		0xFFFFFEFF,		0x0,		REGCLRSETALL},
+	{0x11c,		0xFFFEFFFF,		0x0,		REGCLRSETALL},
+	{0x11c,		0xFEFFFFFF,		0x0,		REGCLRSETALL},
+	{0x120,		0xffffffff,		0x100,		REGCLRSETALL},
+	{0x2d0,		0xffffffff,		0x300,		REGCLRSETALL},
+	{0x2dc,		0xffffffff,		0x300,		REGCLRSETALL},
+	{0x2e8,		0xffffffff,		0x300,		REGCLRSETALL},
 };
 
-static struct ddr_reg_set ddr_cfg1_2g[] = {
-	{0x310,		0x00020000},
-	{0x310,		0x00020001},
-	{0x600,		0x002e0176},
-	{0x604,		0x002e0176},
-	{0x608,		0x001700bb},
-	{0x60c,		0x000b005d},
-	{0x610,		0x0005002e},
-	{0x614,		0x00020017},
-	{0x618,		0x00020017},
-	{0x61c,		0x00020017},
-	{0x678,		0x00000019},
-	{0x100,		0x000000f8},
-	{0x620,		0x03030404},
-	{0x624,		0x04030505},
-	{0x628,		0x07030884},
-	{0x62c,		0x13150401},
-	{0x630,		0x17150604},
-	{0x634,		0x00110000},
-	{0x638,		0x200a0a08},
-	{0x63c,		0x1730f803},
-	{0x640,		0x000a0c00},
-	{0x644,		0xa005000a},
-	{0x648,		0x00000000},
-	{0x64c,		0x00081306},
-	{0x650,		0x04070304},
-	{0x654,		0x00000404},
-	{0x658,		0x00000060},
-	{0x65c,		0x00030008},
-	{0x660,		0x00000000},
-	{0x680,		0x00000603},
-	{0x684,		0x01000202},
-	{0x688,		0x0413040d},
-	{0x68c,		0x20002420},
-	{0x690,		0x00140000},
-	{0x69c,		0x01240074},
-	{0x6a0,		0x00000000},
-	{0x6a4,		0x20240c00},
-	{0x6a8,		0x00040000},
-	{0x4,		0x10010006},
-	{0xc,		0x00000002},
-	{0x4,		0x10020000},
-	{0xc,		0x00000002},
-	{0x4,		0x10030031},
-	{0xc,		0x00000002},
-	{0x4,		0x100b0033},
-	{0xc,		0x00000002},
-	{0x4,		0x10160016},
-	{0xc,		0x00000002},
-	{0x10,		0x00000010},
-	{0x14,		0x00000001},
+static struct ddr_reg_cfg ddr_csr_cfg3[] = {
+	{0x100,		0x0,	0x000000e0,	REGSETALL},
+	{0x620,		0x0,	0x04041417,	REGSETALL},
+	{0x624,		0x0,	0x09110609,	REGSETALL},
+	{0x628,		0x0,	0x442d0994,	REGSETALL},
+	{0x62c,		0x0,	0x271e102b,	REGSETALL},
+	{0x630,		0x0,	0x291b140a,	REGSETALL},
+	{0x634,		0x0,	0x001c0000,	REGSETALL},
+	{0x638,		0x0,	0x200f0f08,	REGSETALL},
+	{0x63c,		0x0,	0x29420a06,	REGSETALL},
+	{0x640,		0x0,	0x019e1fc1,	REGSETALL},
+	{0x644,		0x0,	0x10cb0196,	REGSETALL},
+	{0x648,		0x0,	0x00000000,	REGSETALL},
+	{0x64c,		0x0,	0x00082714,	REGSETALL},
+	{0x650,		0x0,	0x16442f0d,	REGSETALL},
+	{0x654,		0x0,	0x00001916,	REGSETALL},
+	{0x658,		0x0,	0x00000060,	REGSETALL},
+	{0x65c,		0x0,	0x00600020,	REGSETALL},
+	{0x660,		0x0,	0x00000000,	REGSETALL},
+	{0x680,		0x0,	0x0c00040f,	REGSETALL},
+	{0x684,		0x0,	0x03000604,	REGSETALL},
+	{0x688,		0x0,	0x0515040d,	REGSETALL},
+	{0x68c,		0x0,	0x20002c20,	REGSETALL},
+	{0x690,		0x0,	0x00140000,	REGSETALL},
+	{0x69c,		0x0,	0x01240074,	REGSETALL},
+	{0x6a0,		0x0,	0x00000000,	REGSETALL},
+	{0x6a4,		0x0,	0x202c0c00,	REGSETALL},
+	{0x6a8,		0x0,	0x00040000,	REGSETALL},
+	{0x4,		0x0,	0x30010036,	(F_SET | REG4G | REG8G)},
+	{0x4,		0x0,	0x10010036,	(F_SET | REG2G)},
+	{0xc,		0x0,	0x00000002,	REGSETALL},
+	{0x4,		0x0,	0x3002001b,	(F_SET | REG4G | REG8G)},
+	{0x4,		0x0,	0x10010036,	(F_SET | REG2G)},
+	{0xc,		0x0,	0x00000002,	REGSETALL},
+	{0x4,		0x0,	0x30030031,	(F_SET | REG4G | REG8G)},
+	{0x4,		0x0,	0x10030031,	(F_SET | REG2G)},
+	{0xc,		0x0,	0x00000002,	REGSETALL},
+	{0x4,		0x0,	0x300b0066,	(F_SET | REG4G)},
+	{0x4,		0x0,	0x300b0036,	(F_SET | REG8G)},
+	{0x4,		0x0,	0x100b0066,	(F_SET | REG2G)},
+	{0xc,		0x0,	0x00000002,	REGSETALL},
+	{0x4,		0x0,	0x30160016,	(F_SET | REG4G | REG8G)},
+	{0x4,		0x0,	0x10160016,	(F_SET | REG2G)},
+	{0xc,		0x0,	0x00000002,	REGSETALL},
+	{0x410,		0x0,	0x00101010,	REGSETALL},
+	{0x420,		0x0,	0x0c181006,	REGSETALL},
+	{0x424,		0x0,	0x20200820,	REGSETALL},
+	{0x428,		0x0,	0x80000020,	REGSETALL},
+	{0x0,		0x0,	0x00000001,	REGSETALL},
+	{0x108,		0x0,	0x00003000,	REGSETALL},
+	{0x704,		0x0,	0x00000007,	REGSETALL | OFFSET_SEL},
+	{0x330,		0x0,	0x09313fff,	(F_SET | REG4G | REG8G)},
+	{0x330,		0x0,	0x09311fff,	(F_SET | REG2G)},
+	{0x508,		0x0,	0x00000033,	(F_SET | REG4G | REG8G)},
+	{0x508,		0x0,	0x00000013,	(F_SET | REG2G)},
+	{0x324,		0x0,	0x00002000,	REGSETALL},
+	{0x104,		0x0,	0x90000000,	REGSETALL},
+	{0x510,		0x0,	0x00000100,	REGSETALL},
+	{0x514,		0x0,	0x00000000,	REGSETALL},
+	{0x700,		0x0,	0x00000003,	REGSETALL | OFFSET_SEL},
+	{0x514,		0x0,	0x00000600,	REGSETALL},
+	{0x20,		0x0,	0x00000001,	REGSETALL},
 };
 
+static void ddr_csr_set(u32 *csrreg, u32 *secreg, struct ddr_reg_cfg *data,
+		u32 len, u32 mask)
+{
+	u32 *addr;
+	u32 i;
 
-static struct ddr_reg_clrset ddr_cfg2[] = {
-	{46,	~(0xF << 24),	(0x3 << 24)},
-	{33,	~(0x1 << 24),	0x0},
-	{44,	~(0x1 << 16),	0x0},
-	{44,	~(0x1 << 24),	0x0},
-	{45,	0xffffffff,	0x1},
-	{146,	0xffffffff,	(0x3 << 24)},
-	{147,	0xffffffff,	(0x3 << 8)},
-	{147,	0xffffffff,	(0x3 << 24)},
-	{44,	0xffffffff,	(0x1 << 8)},
-	{46,	~(0xF << 16),	(0x3 << 16)},
-	{33,	~(0x1 << 16),	0x0},
-	{43,	~(0x1 << 16),	0x0},
-	{43,	~(0x1 << 24),	0x0},
-	{44,	0xffffffff,	0x1},
-	{146,	0xffffffff,	(0x3 << 16)},
-	{147,	0xffffffff,	0x3},
-	{147,	0xffffffff,	(0x3 << 16)},
-	{148,	0xffffffff,	(0x3 << 24)},
-	{149,	0xffffffff,	(0x3 << 24)},
-	{150,	0xffffffff,	(0x3 << 24)},
-	{43,	0xffffffff,	(0x1 << 8)},
-	{67,	~(0xF << 8),	(0x3 << 8)},
-	{68,	~(0x1 << 8),	0x0},
-	{71,	~(0x1 << 16),	0x0},
-	{71,	~(0x1 << 24),	0x0},
-	{72,	0xffffffff,	(0x1 << 8)},
-	{180,	0xffffffff,	(0x3 << 8)},
-	{183,	0xffffffff,	(0x3 << 8)},
-	{186,	0xffffffff,	(0x3 << 8)},
-};
+	for (i = 0; i < len; i++) {
+		if (!(data[i].flag & mask))
+			continue;
 
-static struct ddr_reg_set ddr_cfg3[] = {
-	{0x100,	0x000000e0},
-	{0x620,	0x04041417},
-	{0x624,	0x09110609},
-	{0x628,	0x442d0994},
-	{0x62c,	0x271e102b},
-	{0x630,	0x291b140a},
-	{0x634,	0x001c0000},
-	{0x638,	0x200f0f08},
-	{0x63c,	0x29420a06},
-	{0x640,	0x019e1fc1},
-	{0x644,	0x10cb0196},
-	{0x648,	0x00000000},
-	{0x64c,	0x00082714},
-	{0x650,	0x16442f0d},
-	{0x654,	0x00001916},
-	{0x658,	0x00000060},
-	{0x65c,	0x00600020},
-	{0x660,	0x00000000},
-	{0x680,	0x0c00040f},
-	{0x684,	0x03000604},
-	{0x688,	0x0515040d},
-	{0x68c,	0x20002c20},
-	{0x690,	0x00140000},
-	{0x69c,	0x01240074},
-	{0x6a0,	0x00000000},
-	{0x6a4,	0x202c0c00},
-	{0x6a8,	0x00040000},
-	{0x4,	0x30010036},
-	{0xc,	0x00000002},
-	{0x4,	0x3002001b},
-	{0xc,	0x00000002},
-	{0x4,	0x30030031},
-	{0xc,	0x00000002},
-	{0x4,	0x300b0066},
-	{0xc,	0x00000002},
-	{0x4,	0x30160016},
-	{0xc,	0x00000002},
-	{0x410,	0x00101010},
-	{0x420,	0x0c181006},
-	{0x424,	0x20200820},
-	{0x428,	0x80000020},
-	{0x0,	0x00000001},
-	{0x108,	0x00003000},
-	{DDRSEC_SEL | 0x704,	0x00000007},
-	{0x330,	0x09313fff},
-	{0x508,	0x00000033},
-	{0x324,	0x00002000},
-	{0x104,	0x90000000},
-	{0x510,	0x00000100},
-	{0x514,	0x00000000},
-	{DDRSEC_SEL | 0x700,	0x00000003},
-	{0x514,	0x00000600},
-	{0x20,	0x00000001},
-};
+		if (data[i].flag & OFFSET_SEL)
+			addr = secreg + REGOFFSET(data[i].offset);
+		else
+			addr = csrreg + REGOFFSET(data[i].offset);
 
-static struct ddr_reg_set ddr_cfg3_2g[] = {
-	{0x100,	0x000000e0},
-	{0x620,	0x04041417},
-	{0x624,	0x09110609},
-	{0x628,	0x442d0994},
-	{0x62c,	0x271e102b},
-	{0x630,	0x291b140a},
-	{0x634,	0x001c0000},
-	{0x638,	0x200f0f08},
-	{0x63c,	0x29420a06},
-	{0x640,	0x019e1fc1},
-	{0x644,	0x10cb0196},
-	{0x648,	0x00000000},
-	{0x64c,	0x00082714},
-	{0x650,	0x16442f0d},
-	{0x654,	0x00001916},
-	{0x658,	0x00000060},
-	{0x65c,	0x00600020},
-	{0x660,	0x00000000},
-	{0x680,	0x0c00040f},
-	{0x684,	0x03000604},
-	{0x688,	0x0515040d},
-	{0x68c,	0x20002c20},
-	{0x690,	0x00140000},
-	{0x69c,	0x01240074},
-	{0x6a0,	0x00000000},
-	{0x6a4,	0x202c0c00},
-	{0x6a8,	0x00040000},
-	{0x4,	0x10010036},
-	{0xc,	0x00000002},
-	{0x4,	0x10010036},
-	{0xc,	0x00000002},
-	{0x4,	0x10030031},
-	{0xc,	0x00000002},
-	{0x4,	0x100b0066},
-	{0xc,	0x00000002},
-	{0x4,	0x10160016},
-	{0xc,	0x00000002},
-	{0x410,	0x00101010},
-	{0x420,	0x0c181006},
-	{0x424,	0x20200820},
-	{0x428,	0x80000020},
-	{0x0,	0x00000001},
-	{0x108,	0x00003000},
-	{DDRSEC_SEL | 0x704,	0x00000007},
-	{0x330, 0x09311fff},
-	{0x508, 0x00000013},
-	{0x324,	0x00002000},
-	{0x104,	0x90000000},
-	{0x510,	0x00000100},
-	{0x514,	0x00000000},
-	{DDRSEC_SEL | 0x700,	0x00000003},
-	{0x514,	0x00000600},
-	{0x20,	0x00000001},
-};
+		if (data[i].flag & F_CLRSET)
+			DDR_REG_TRIGGER(addr, data[i].mask, data[i].val);
+		else
+			out_le32(addr, data[i].val);
+	}
+}
 
 void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size)
 {
-	u32 i, len;
-	u32 *addr;
+	u32 len;
 	u32 val;
-	struct ddr_reg_set *cfg;
+	u32 mask;
 
 	switch (size) {
 	case DDR_SIZE_2G:
-		len = sizeof(ddr_cfg_2g)/sizeof(struct ddr_reg_set);
-		cfg = ddr_cfg_2g;
+		mask = REG2G;
 		break;
+
 	case DDR_SIZE_4G:
-		len = sizeof(ddr_cfg)/sizeof(struct ddr_reg_set);
-		cfg = ddr_cfg;
+		mask = REG4G;
 		break;
+
 	case DDR_SIZE_8G:
+		mask = REG8G;
+		break;
+
 	case DDR_SIZE_16G:
 	default:
 		return;
 	};
 
-	for (i = 0; i < len; i++) {
-		if (cfg[i].offset & DDRSEC_SEL)
-			addr = secreg + REGOFFSET(cfg[i].offset & (~DDRSEC_SEL));
-		else
-			addr = csrreg + REGOFFSET(cfg[i].offset);
-		out_le32(addr, cfg[i].val);
-	}
+	len = sizeof(ddr_csr_cfg)/sizeof(struct ddr_reg_cfg);
+	ddr_csr_set(csrreg, secreg, ddr_csr_cfg, len, mask);
 
 	do {
 		udelay(1);
@@ -346,10 +252,10 @@ void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size)
 	case DDR_SIZE_2G:
 		out_le32(csrreg + REGOFFSET(0x10), 0x0000001c);
 		break;
+	case DDR_SIZE_8G:
 	case DDR_SIZE_4G:
 		out_le32(csrreg + REGOFFSET(0x10), 0x0000003c);
 		break;
-	case DDR_SIZE_8G:
 	case DDR_SIZE_16G:
 	default:
 		break;
@@ -357,23 +263,8 @@ void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size)
 	out_le32(csrreg + REGOFFSET(0x14), 0x00000001);
 	udelay(4);
 
-	switch (size) {
-	case DDR_SIZE_2G:
-		len = sizeof(ddr_cfg1_2g)/sizeof(struct ddr_reg_set);
-		cfg = ddr_cfg1_2g;
-		break;
-	case DDR_SIZE_4G:
-		len = sizeof(ddr_cfg1)/sizeof(struct ddr_reg_set);
-		cfg = ddr_cfg1;
-		break;
-	case DDR_SIZE_8G:
-	case DDR_SIZE_16G:
-	default:
-		return;
-	};
-
-	for (i = 0; i < len; i++)
-		out_le32(csrreg + REGOFFSET(cfg[i].offset), cfg[i].val);
+	len = sizeof(ddr_csr_cfg1)/sizeof(struct ddr_reg_cfg);
+	ddr_csr_set(csrreg, secreg, ddr_csr_cfg1, len, mask);
 
 	udelay(4);
 	out_le32(csrreg + REGOFFSET(0x10), 0x00000011);
@@ -381,15 +272,14 @@ void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size)
 
 	switch (size) {
 	case DDR_SIZE_4G:
+	case DDR_SIZE_8G:
 		out_le32(csrreg + REGOFFSET(0x10), 0x00000020);
 		out_le32(csrreg + REGOFFSET(0x14), 0x00000001);
-
 		udelay(4);
 		out_le32(csrreg + REGOFFSET(0x10), 0x00000021);
 		out_le32(csrreg + REGOFFSET(0x14), 0x00000001);
 		break;
 	case DDR_SIZE_2G:
-	case DDR_SIZE_8G:
 	case DDR_SIZE_16G:
 	default:
 		break;
@@ -407,16 +297,13 @@ void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size)
 		if ((val & 0x20) == 0x20) {
 			switch (val & 0x0000001f) {
 			case 0: //ddrc_clock=12M
-				clrsetbits_le32(CLK_DDR_BUS_REG,
-					CLK_DDR_BUS_MASK, 0<<24);
+				DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
 				break;
 			case 1: //ddrc_clock=200M
-				clrsetbits_le32(CLK_DDR_BUS_REG,
-					CLK_DDR_BUS_MASK, 3<<24);
+				DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV8);
 				break;
 			case 2: //ddrc_clock=800M
-				clrsetbits_le32(CLK_DDR_BUS_REG,
-					CLK_DDR_BUS_MASK, 1<<24);
+				DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV2);
 				break;
 			default:
 				break;
@@ -436,35 +323,9 @@ void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size)
 	val = in_le32(phyreg + 2048 + 84);
 	out_le32((phyreg + 2048 + 84), val & 0xF8000000);
 
-	len = sizeof(ddr_cfg2) / sizeof(struct ddr_reg_clrset);
-	for (i = 0; i < len; i++) {
-		addr = phyreg + 2048;
-		addr += ddr_cfg2[i].offset;
-		DDR_REG_TRIGGER(addr, ddr_cfg2[i].mask, ddr_cfg2[i].val);
-	}
-
-	switch (size) {
-	case DDR_SIZE_2G:
-		len = sizeof(ddr_cfg3_2g)/sizeof(struct ddr_reg_set);
-		cfg = ddr_cfg3_2g;
-		break;
-	case DDR_SIZE_4G:
-		len = sizeof(ddr_cfg3)/sizeof(struct ddr_reg_set);
-		cfg = ddr_cfg3;
-		break;
-	case DDR_SIZE_8G:
-	case DDR_SIZE_16G:
-	default:
-		return;
-	};
-
-	for (i = 0; i < len; i++) {
-		if (cfg[i].offset & DDRSEC_SEL)
-			addr = secreg + REGOFFSET(cfg[i].offset & (~DDRSEC_SEL));
-		else
-			addr = csrreg + REGOFFSET(cfg[i].offset);
+	len = sizeof(ddr_csr_cfg2)/sizeof(struct ddr_reg_cfg);
+	ddr_csr_set((phyreg + PHY_BASE_ADDR), secreg, ddr_csr_cfg2, len, mask);
 
-		out_le32(addr, cfg[i].val);
-	}
+	len = sizeof(ddr_csr_cfg3)/sizeof(struct ddr_reg_cfg);
+	ddr_csr_set(csrreg, secreg, ddr_csr_cfg3, len, mask);
 }
-
diff --git a/drivers/ram/starfive/ddrphy_start.c b/drivers/ram/starfive/ddrphy_start.c
index 45d6906a9e..edfd43bb42 100644
--- a/drivers/ram/starfive/ddrphy_start.c
+++ b/drivers/ram/starfive/ddrphy_start.c
@@ -5,303 +5,276 @@
  * Author:	yanhong <yanhong.wang@starfivetech.com>
  *
  */
+#include <common.h>
+#include <asm/io.h>
 
 #include "starfive_ddr.h"
 
-#define G_SPEED_2133	1
-
-#define OFFSET_SEL	0x80000000
-#define DDR_2G_MASK	0x40000000
-
-static struct ddr_reg_clrset ddr_start_data[] = {
-	{(OFFSET_SEL | 89),  	0xffffff00,  	0x00000051},
-	{(OFFSET_SEL | 78),  	0xfffffcff,  	0x0},
-	{(OFFSET_SEL | 345),  	0xffffff00,  	0x00000051},
-	{(OFFSET_SEL | 334), 	0xfffffcff, 	0x0},
-	{(OFFSET_SEL | 601), 	0xffffff00, 	0x00000051},
-	{(OFFSET_SEL | 590), 	0xfffffcff, 	0x0},
-	{(OFFSET_SEL | 857), 	0xffffff00, 	0x00000051},
-	{(OFFSET_SEL | 846), 	0xfffffcff, 	0x0},
-	{(OFFSET_SEL | 1793), 	0xfffffeff, 	0x0},
-	{(OFFSET_SEL | 1793), 	0xfffcffff, 	0x0},
-	{(OFFSET_SEL | 125), 	0xfff0ffff, 	0x00010000},
-	{(OFFSET_SEL | 102), 	0xfffffffc, 	0x00000001},
-	{(OFFSET_SEL | 105), 	0xffffffe0, 	0x00000001},
-	{(OFFSET_SEL | 92), 	0xfffffffe, 	0x00000001},
-	{(OFFSET_SEL | 94), 	0xffffe0ff, 	0x00000200},
-	{(OFFSET_SEL | 96), 	0xfffff0ff, 	0x00000400},
-	{(OFFSET_SEL | 89), 	0xffffff00, 	0x00000051},
-	{(OFFSET_SEL | 381), 	0xfff0ffff, 	0x00010000},
-	{(OFFSET_SEL | 358), 	0xfffffffc, 	0x00000001},
-	{(OFFSET_SEL | 361), 	0xffffffe0, 	0x00000001},
-	{(OFFSET_SEL | 348), 	0xfffffffe, 	0x00000001},
-	{(OFFSET_SEL | 350), 	0xffffe0ff, 	0x00000200},
-	{(OFFSET_SEL | 352),  	0xfffff0ff,	0x00000400},
-	{(OFFSET_SEL | 345), 	0xffffff00,	0x00000051},
-	{(OFFSET_SEL | 637), 	0xfff0ffff,	0x00010000},
-	{(OFFSET_SEL | 614), 	0xfffffffc,	0x00000001},
-	{(OFFSET_SEL | 617), 	0xffffffe0,	0x00000001},
-	{(OFFSET_SEL | 604), 	0xfffffffe,	0x00000001},
-	{(OFFSET_SEL | 606), 	0xffffe0ff,	0x00000200},
-	{(OFFSET_SEL | 608), 	0xfffff0ff,	0x00000400},
-	{(OFFSET_SEL | 601), 	0xffffff00,	0x00000051},
-	{(OFFSET_SEL | 893), 	0xfff0ffff,	0x00010000},
-	{(OFFSET_SEL | 870), 	0xfffffffc,	0x00000001},
-	{(OFFSET_SEL | 873), 	0xffffffe0,	0x00000001},
-	{(OFFSET_SEL | 860), 	0xfffffffe,	0x00000001},
-	{(OFFSET_SEL | 862), 	0xffffe0ff,	0x00000200},
-	{(OFFSET_SEL | 864), 	0xfffff0ff,	0x00000400},
-	{(OFFSET_SEL | 857), 	0xffffff00,	0x00000051},
-	{(OFFSET_SEL | 1895), 	0xffffe000,	0x00001342},
-	{(OFFSET_SEL | 1835), 	0xfffff0ff,	0x00000200},
-	{(OFFSET_SEL | 1793), 	0xfffffeff,	0x00000100},
-	{62, 	0xfffffeff,	0x0},
-	{66, 	0xfffffeff,	0x0},
-	{166, 	0xffffff80,	0x00000001},
-	{62, 	0xfff0ffff,	0x00010000},
-	{62, 	0xf0ffffff,	0x01000000},
-	{166, 	0xffff80ff,	0x00000100},
-	{179, 	0xff80ffff,	0x00010000},
-	{67, 	0xffe0ffff,	0x00010000},
-	{67, 	0xe0ffffff,	0x01000000},
-	{179, 	0x80ffffff,	0x01000000},
-	{166, 	0xff80ffff,	0x00010000},
-	{62, 	0xfff0ffff,	0x00010000},
-	{62, 	0xf0ffffff,	0x01000000},
-	{166, 	0x80ffffff,	0x01000000},
-	{182, 	0xff80ffff,	0x00010000},
-	{67, 	0xffe0ffff,	0x00010000},
-	{67,	0xe0ffffff,	0x01000000},
-	{182, 	0x80ffffff,	0x01000000},
-	{167, 	0xffffff80,	0x00000017},
-	{62, 	0xfff0ffff,	0x00010000},
-	{62, 	0xf0ffffff,	0x01000000},
-	{167, 	0xffff80ff,	0x00001700},
-	{185, 	0xff80ffff,	0x00200000},
-	{67, 	0xffe0ffff,	0x00010000},
-	{67, 	0xe0ffffff,	0x01000000},
-	{185, 	0x80ffffff,	0x20000000},
-	{10, 	0xffffffe0,	0x00000002},
-	{0, 	0xfffffffe,	0x00000001},
-#ifdef G_DDR_SIMULATION
-	{(OFFSET_SEL | 1860),	0x80ffffff,	0x01000000},
-#endif
-	{11 | DDR_2G_MASK,	0xfffffff0,	0x00000005},
-	{247,	0xffffffff,	0x00000008},
-	{249,	0xffffffff,	0x00000800},
-	{252,	0xffffffff,	0x00000008},
-	{254,	0xffffffff,	0x00000800},
-	{281,	0xffffffff,	0x33000000},
-	{305,	0xffffffff,	0x33000000},
-	{329,	0xffffffff,	0x33000000},
-	{353,	0xffffffff,	0x33000000},
-	{289,	0xffffffff,	0x66000000},
-	{313,	0xffffffff,	0x66000000},
-	{337,	0xffffffff,	0x66000000},
-	{361,	0xffffffff,	0x66000000},
-	{282,	0xffffffff,	0x00160000},
-	{306,	0xffffffff,	0x00160000},
-	{330,	0xffffffff,	0x00160000},
-	{354,	0xffffffff,	0x00160000},
-	{290,	0xffffffff,	0x00160000},
-	{314,	0xffffffff,	0x00160000},
-	{338,	0xffffffff,	0x00160000},
-	{362,	0xffffffff,	0x00160000},
-	{282,	0xffffff00,	0x17},
-	{306,	0xffffff00,	0x17},
-	{330,	0xffffff00,	0x17},
-	{354,	0xffffff00,	0x17},
-	{290,	0xffffff00,	0x17},
-	{314,	0xffffff00,	0x17},
-	{338,	0xffffff00,	0x17},
-	{362,	0xffffff00,	0x17},
-	{282,	0xffff00ff,	0x2000},
-	{306,	0xffff00ff,	0x2000},
-	{330,	0xffff00ff,	0x2000},
-	{354,	0xffff00ff,	0x2000},
-	{290,	0xffff00ff,	0x2000},
-	{314,	0xffff00ff,	0x2000},
-	{338,	0xffff00ff,	0x2000},
-	{362,	0xffff00ff,	0x2000},
-	{(OFFSET_SEL | 65), 	0xffffffff,	0x00000100},
-	{(OFFSET_SEL | 321),	0xffffffff,	0x00000100},
-	{(OFFSET_SEL | 577),	0xffffffff,	0x00000100},
-	{(OFFSET_SEL | 833),	0xffffffff,	0x00000100},
-};
-
-static struct ddr_reg_clrset ddr_start_data1[] = {
-#ifdef G_SPEED_3200
-	{96, 	0xff00ffff,	0x00180000},
-	{352,	0xff00ffff,	0x00180000},
-	{608,	0xff00ffff,	0x00180000},
-	{864,	0xff00ffff,	0x00180000},
-#elif defined G_SPEED_2666
-	{96, 	0xff00ffff,	0x00140000},
-	{352,	0xff00ffff,	0x00140000},
-	{608,	0xff00ffff,	0x00140000},
-	{864,	0xff00ffff,	0x00140000},
-#elif defined G_SPEED_2133
-	{96, 	0xff00ffff,	0x00120000},
-	{352,	0xff00ffff,	0x00120000},
-	{608,	0xff00ffff,	0x00120000},
-	{864,	0xff00ffff,	0x00120000},
-#endif
-	{33,  	0xffffff00,	0x0040},
-	{289, 	0xffffff00,	0x0040},
-	{545, 	0xffffff00,	0x0040},
-	{801, 	0xffffff00,	0x0040},
-	{1038,	0xfcffffff,	0x03000000},
-	{1294,	0xfcffffff,	0x03000000},
-	{1550,	0xfcffffff,	0x03000000},
-	{83,  	0xffc0ffff,	0x70000},
-	{339, 	0xffc0ffff,	0x70000},
-	{595, 	0xffc0ffff,	0x70000},
-	{851, 	0xffc0ffff,	0x70000},
-	{1062,	0xf800ffff,	0x70000},
-	{1318,	0xf800ffff,	0x70000},
-	{1574,	0xf800ffff,	0x70000},
-	{1892,	0xfffc0000,	0x15547},
-	{1893,	0xfffc0000,	0x7},
-	{1852,	0xffffe000,	0x07a},
-	{1853,	0xffffffff,	0x0100},
-	{1822,	0xffffffff,	0xFF},
-	{1896,	0xfffffc00,	0x03d5},
-	{91,  	0xfc00ffff,	0x03d50000},
-	{347, 	0xfc00ffff,	0x03d50000},
-	{603, 	0xfc00ffff,	0x03d50000},
-	{859, 	0xfc00ffff,	0x03d50000},
-};
-
-static struct ddr_reg_set ddr_start_data2[] = {
-
-	{1912,	0xcc3bfc7},
-	{1913,	0xff8f},
-	{1914,	0x33f07ff},
-	{1915,	0xc3c37ff},
-	{1916,	0x1fffff10},
-	{1917,	0x230070},
-	{1918,	0x3ff7ffff},
-	{1919,	0xe10},
-	{1920,	0x1fffffff},
-	{1921,	0x188411},
-	{1922,	0x1fffffff},
-	{1923,	0x180400},
-	{1924,	0x1fffffff},
-	{1925,	0x180400},
-	{1926,	0x1fffffcf},
-	{1927,	0x188400},
-	{1928,	0x1fffffff},
-	{1929,	0x4188411},
-	{1837,	0x24410},
-	{1840,	0x24410},
-	{1842,	0x2ffff},
-};
-
-static struct ddr_reg_clrset ddr_start_data3[] = {
-	{76,	0xff0000f8,	0x00ff8f07},
-	{332,	0xff0000f8,	0x00ff8f07},
-	{588,	0xff0000f8,	0x00ff8f07},
-	{844,	0xff0000f8,	0x00ff8f07},
-	{77,	0xffff0000,	0xff8f},
-	{333,	0xffff0000,	0xff8f},
-	{589,	0xffff0000,	0xff8f},
-	{845,	0xffff0000,	0xff8f},
-	{1062,	0xffffff00,	0xff},
-	{1318,	0xffffff00,	0xff},
-	{1574,	0xffffff00,	0xff},
-	{1028,	0xffffffff,	0x1000000},
-	{1284,	0xffffffff,	0x1000000},
-	{1540,	0xffffffff,	0x1000000},
-};
-
-static struct ddr_reg_clrset ddr_start_data4[] = {
-	{130,	0x0000ffff,	0xffff0000},
-	{386,	0x0000ffff,	0xffff0000},
-	{642,	0x0000ffff,	0xffff0000},
-	{898,	0x0000ffff,	0xffff0000},
-	{131,	0xfffffff0,	0xf},
-	{387,	0xfffffff0,	0xf},
-	{643,	0xfffffff0,	0xf},
-	{899,	0xfffffff0,	0xf},
-	{29,	0xc0ffffff,	0x10000000},
-	{285,	0xc0ffffff,	0x10000000},
-	{541,	0xc0ffffff,	0x10000000},
-	{797,	0xc0ffffff,	0x10000000},
-	{30,	0xffffffff,	0x00080000},
-	{286,	0xffffffff,	0x00080000},
-	{542,	0xffffffff,	0x00080000},
-	{798,	0xffffffff,	0x00080000},
-	{31,	0xffffffc0,	0x00000010},
-	{287,	0xffffffc0,	0x00000010},
-	{543,	0xffffffc0,	0x00000010},
-	{799,	0xffffffc0,	0x00000010},
-	{1071,	0xfffffff0,	0x00000008},
-	{1327,	0xfffffff0,	0x00000008},
-	{1583,	0xfffffff0,	0x00000008},
-	{1808,	0xfffffff0,	0x00000008},
-	{1896,	0xfff0ffff,	0x00080000},
+static struct ddr_reg_cfg ddr_start_cfg[] = {
+	{89,	0xffffff00,	0x00000051,	(OFFSET_SEL | REGCLRSETALL)},
+	{78,	0xfffffcff,	0x0,		(OFFSET_SEL | REGCLRSETALL)},
+	{345,	0xffffff00,	0x00000051,	(OFFSET_SEL | REGCLRSETALL)},
+	{334,	0xfffffcff,	0x0,		(OFFSET_SEL | REGCLRSETALL)},
+	{601,	0xffffff00,	0x00000051,	(OFFSET_SEL | REGCLRSETALL)},
+	{590,	0xfffffcff,	0x0,		(OFFSET_SEL | REGCLRSETALL)},
+	{857,	0xffffff00,	0x00000051,	(OFFSET_SEL | REGCLRSETALL)},
+	{846,	0xfffffcff,	0x0,		(OFFSET_SEL | REGCLRSETALL)},
+	{1793,	0xfffffeff,	0x0,		(OFFSET_SEL | REGCLRSETALL)},
+	{1793,	0xfffcffff,	0x0,		(OFFSET_SEL | REGCLRSETALL)},
+	{125,	0xfff0ffff,	0x00010000,	(OFFSET_SEL | REGCLRSETALL)},
+	{102,	0xfffffffc,	0x00000001,	(OFFSET_SEL | REGCLRSETALL)},
+	{105,	0xffffffe0,	0x00000001,	(OFFSET_SEL | REGCLRSETALL)},
+	{92,	0xfffffffe,	0x00000001,	(OFFSET_SEL | REGCLRSETALL)},
+	{94,	0xffffe0ff,	0x00000200,	(OFFSET_SEL | REGCLRSETALL)},
+	{96,	0xfffff0ff,	0x00000400,	(OFFSET_SEL | REGCLRSETALL)},
+	{89,	0xffffff00,	0x00000051,	(OFFSET_SEL | REGCLRSETALL)},
+	{381,	0xfff0ffff,	0x00010000,	(OFFSET_SEL | REGCLRSETALL)},
+	{358,	0xfffffffc,	0x00000001,	(OFFSET_SEL | REGCLRSETALL)},
+	{361,	0xffffffe0,	0x00000001,	(OFFSET_SEL | REGCLRSETALL)},
+	{348,	0xfffffffe,	0x00000001,	(OFFSET_SEL | REGCLRSETALL)},
+	{350,	0xffffe0ff,	0x00000200,	(OFFSET_SEL | REGCLRSETALL)},
+	{352,	0xfffff0ff,	0x00000400,	(OFFSET_SEL | REGCLRSETALL)},
+	{345,	0xffffff00,	0x00000051,	(OFFSET_SEL | REGCLRSETALL)},
+	{637,	0xfff0ffff,	0x00010000,	(OFFSET_SEL | REGCLRSETALL)},
+	{614,	0xfffffffc,	0x00000001,	(OFFSET_SEL | REGCLRSETALL)},
+	{617,	0xffffffe0,	0x00000001,	(OFFSET_SEL | REGCLRSETALL)},
+	{604,	0xfffffffe,	0x00000001,	(OFFSET_SEL | REGCLRSETALL)},
+	{606,	0xffffe0ff,	0x00000200,	(OFFSET_SEL | REGCLRSETALL)},
+	{608,	0xfffff0ff,	0x00000400,	(OFFSET_SEL | REGCLRSETALL)},
+	{601,	0xffffff00,	0x00000051,	(OFFSET_SEL | REGCLRSETALL)},
+	{893,	0xfff0ffff,	0x00010000,	(OFFSET_SEL | REGCLRSETALL)},
+	{870,	0xfffffffc,	0x00000001,	(OFFSET_SEL | REGCLRSETALL)},
+	{873,	0xffffffe0,	0x00000001,	(OFFSET_SEL | REGCLRSETALL)},
+	{860,	0xfffffffe,	0x00000001,	(OFFSET_SEL | REGCLRSETALL)},
+	{862,	0xffffe0ff,	0x00000200,	(OFFSET_SEL | REGCLRSETALL)},
+	{864,	0xfffff0ff,	0x00000400,	(OFFSET_SEL | REGCLRSETALL)},
+	{857,	0xffffff00,	0x00000051,	(OFFSET_SEL | REGCLRSETALL)},
+	{1895,	0xffffe000,	0x00001342,	(OFFSET_SEL | REGCLRSETALL)},
+	{1835,	0xfffff0ff,	0x00000200,	(OFFSET_SEL | REGCLRSETALL)},
+	{1793,	0xfffffeff,	0x00000100,	(OFFSET_SEL | REGCLRSETALL)},
+	{62,	0xfffffeff,	0x0,		REGCLRSETALL},
+	{66,	0xfffffeff,	0x0,		REGCLRSETALL},
+	{166,	0xffffff80,	0x00000001,	REGCLRSETALL},
+	{62,	0xfff0ffff,	0x00010000,	REGCLRSETALL},
+	{62,	0xf0ffffff,	0x01000000,	REGCLRSETALL},
+	{166,	0xffff80ff,	0x00000100,	REGCLRSETALL},
+	{179,	0xff80ffff,	0x00010000,	REGCLRSETALL},
+	{67,	0xffe0ffff,	0x00010000,	REGCLRSETALL},
+	{67,	0xe0ffffff,	0x01000000,	REGCLRSETALL},
+	{179,	0x80ffffff,	0x01000000,	REGCLRSETALL},
+	{166,	0xff80ffff,	0x00010000,	REGCLRSETALL},
+	{62,	0xfff0ffff,	0x00010000,	REGCLRSETALL},
+	{62,	0xf0ffffff,	0x01000000,	REGCLRSETALL},
+	{166,	0x80ffffff,	0x01000000,	REGCLRSETALL},
+	{182,	0xff80ffff,	0x00010000,	REGCLRSETALL},
+	{67,	0xffe0ffff,	0x00010000,	REGCLRSETALL},
+	{67,	0xe0ffffff,	0x01000000,	REGCLRSETALL},
+	{182,	0x80ffffff,	0x01000000,	REGCLRSETALL},
+	{167,	0xffffff80,	0x00000017,	REGCLRSETALL},
+	{62,	0xfff0ffff,	0x00010000,	REGCLRSETALL},
+	{62,	0xf0ffffff,	0x01000000,	REGCLRSETALL},
+	{167,	0xffff80ff,	0x00001700,	REGCLRSETALL},
+	{185,	0xff80ffff,	0x00200000,	REGCLRSETALL},
+	{67,	0xffe0ffff,	0x00010000,	REGCLRSETALL},
+	{67,	0xe0ffffff,	0x01000000,	REGCLRSETALL},
+	{185,	0x80ffffff,	0x20000000,	REGCLRSETALL},
+	{10,	0xffffffe0,	0x00000002,	REGCLRSETALL},
+	{0,	0xfffffffe,	0x00000001,	REGCLRSETALL},
+	{11,	0xfffffff0,	0x00000005,	(F_CLRSET | REG2G)},
+	{247,	0xffffffff,	0x00000008,	REGCLRSETALL},
+	{249,	0xffffffff,	0x00000800,	REGCLRSETALL},
+	{252,	0xffffffff,	0x00000008,	REGCLRSETALL},
+	{254,	0xffffffff,	0x00000800,	REGCLRSETALL},
+	{281,	0xffffffff,	0x33000000,	REGCLRSETALL},
+	{305,	0xffffffff,	0x33000000,	REGCLRSETALL},
+	{329,	0xffffffff,	0x33000000,	REGCLRSETALL},
+	{353,	0xffffffff,	0x33000000,	REGCLRSETALL},
+	{289,	0xffffffff,	0x36000000,	(F_CLRSET | REG8G)},
+	{313,	0xffffffff,	0x36000000,	(F_CLRSET | REG8G)},
+	{337,	0xffffffff,	0x36000000,	(F_CLRSET | REG8G)},
+	{361,	0xffffffff,	0x36000000,	(F_CLRSET | REG8G)},
+	{289,	0xffffffff,	0x66000000,	(F_CLRSET | REG2G | REG4G)},
+	{313,	0xffffffff,	0x66000000,	(F_CLRSET | REG2G | REG4G)},
+	{337,	0xffffffff,	0x66000000,	(F_CLRSET | REG2G | REG4G)},
+	{361,	0xffffffff,	0x66000000,	(F_CLRSET | REG2G | REG4G)},
+	{282,	0xffffffff,	0x00160000,	REGCLRSETALL},
+	{306,	0xffffffff,	0x00160000,	REGCLRSETALL},
+	{330,	0xffffffff,	0x00160000,	REGCLRSETALL},
+	{354,	0xffffffff,	0x00160000,	REGCLRSETALL},
+	{290,	0xffffffff,	0x00160000,	REGCLRSETALL},
+	{314,	0xffffffff,	0x00160000,	REGCLRSETALL},
+	{338,	0xffffffff,	0x00160000,	REGCLRSETALL},
+	{362,	0xffffffff,	0x00160000,	REGCLRSETALL},
+	{282,	0xffffff00,	0x17,		REGCLRSETALL},
+	{306,	0xffffff00,	0x17,		REGCLRSETALL},
+	{330,	0xffffff00,	0x17,		REGCLRSETALL},
+	{354,	0xffffff00,	0x17,		REGCLRSETALL},
+	{290,	0xffffff00,	0x17,		REGCLRSETALL},
+	{314,	0xffffff00,	0x17,		REGCLRSETALL},
+	{338,	0xffffff00,	0x17,		REGCLRSETALL},
+	{362,	0xffffff00,	0x17,		REGCLRSETALL},
+	{282,	0xffff00ff,	0x2000,		REGCLRSETALL},
+	{306,	0xffff00ff,	0x2000,		REGCLRSETALL},
+	{330,	0xffff00ff,	0x2000,		REGCLRSETALL},
+	{354,	0xffff00ff,	0x2000,		REGCLRSETALL},
+	{290,	0xffff00ff,	0x2000,		REGCLRSETALL},
+	{314,	0xffff00ff,	0x2000,		REGCLRSETALL},
+	{338,	0xffff00ff,	0x2000,		REGCLRSETALL},
+	{362,	0xffff00ff,	0x2000,		REGCLRSETALL},
+	{65,	0xffffffff,	0x00000100,	(OFFSET_SEL | REGCLRSETALL)},
+	{321,	0xffffffff,	0x00000100,	(OFFSET_SEL | REGCLRSETALL)},
+	{577,	0xffffffff,	0x00000100,	(OFFSET_SEL | REGCLRSETALL)},
+	{833,	0xffffffff,	0x00000100,	(OFFSET_SEL | REGCLRSETALL)},
+	{96,	0x0,		0x300,		(OFFSET_SEL | REGADDSETALL)},
+	{352,	0x0,		0x300,		(OFFSET_SEL | REGADDSETALL)},
+	{608,	0x0,		0x300,		(OFFSET_SEL | REGADDSETALL)},
+	{864,	0x0,		0x300,		(OFFSET_SEL | REGADDSETALL)},
+	{96,	0xff00ffff,	0x00120000,	(OFFSET_SEL | REGCLRSETALL)},
+	{352,	0xff00ffff,	0x00120000,	(OFFSET_SEL | REGCLRSETALL)},
+	{608,	0xff00ffff,	0x00120000,	(OFFSET_SEL | REGCLRSETALL)},
+	{864,	0xff00ffff,	0x00120000,	(OFFSET_SEL | REGCLRSETALL)},
+	{33,	0xffffff00,	0x0040,		(OFFSET_SEL | REGCLRSETALL)},
+	{289,	0xffffff00,	0x0040,		(OFFSET_SEL | REGCLRSETALL)},
+	{545,	0xffffff00,	0x0040,		(OFFSET_SEL | REGCLRSETALL)},
+	{801,	0xffffff00,	0x0040,		(OFFSET_SEL | REGCLRSETALL)},
+	{1038,	0xfcffffff,	0x03000000,	(OFFSET_SEL | REGCLRSETALL)},
+	{1294,	0xfcffffff,	0x03000000,	(OFFSET_SEL | REGCLRSETALL)},
+	{1550,	0xfcffffff,	0x03000000,	(OFFSET_SEL | REGCLRSETALL)},
+	{83,	0xffc0ffff,	0x70000,	(OFFSET_SEL | REGCLRSETALL)},
+	{339,	0xffc0ffff,	0x70000,	(OFFSET_SEL | REGCLRSETALL)},
+	{595,	0xffc0ffff,	0x70000,	(OFFSET_SEL | REGCLRSETALL)},
+	{851,	0xffc0ffff,	0x70000,	(OFFSET_SEL | REGCLRSETALL)},
+	{1062,	0xf800ffff,	0x70000,	(OFFSET_SEL | REGCLRSETALL)},
+	{1318,	0xf800ffff,	0x70000,	(OFFSET_SEL | REGCLRSETALL)},
+	{1574,	0xf800ffff,	0x70000,	(OFFSET_SEL | REGCLRSETALL)},
+	{1892,	0xfffc0000,	0x15547,	(OFFSET_SEL | REGCLRSETALL)},
+	{1893,	0xfffc0000,	0x7,		(OFFSET_SEL | REGCLRSETALL)},
+	{1852,	0xffffe000,	0x07a,		(OFFSET_SEL | REGCLRSETALL)},
+	{1853,	0xffffffff,	0x0100,		(OFFSET_SEL | REGCLRSETALL)},
+	{1822,	0xffffffff,	0xFF,		(OFFSET_SEL | REGCLRSETALL)},
+	{1896,	0xfffffc00,	0x03d5,		(OFFSET_SEL | REGCLRSETALL)},
+	{91,	0xfc00ffff,	0x03d50000,	(OFFSET_SEL | REGCLRSETALL)},
+	{347,	0xfc00ffff,	0x03d50000,	(OFFSET_SEL | REGCLRSETALL)},
+	{603,	0xfc00ffff,	0x03d50000,	(OFFSET_SEL | REGCLRSETALL)},
+	{859,	0xfc00ffff,	0x03d50000,	(OFFSET_SEL | REGCLRSETALL)},
+	{1912,	0x0,		0xcc3bfc7,	(OFFSET_SEL | REGSETALL)},
+	{1913,	0x0,		0xff8f,		(OFFSET_SEL | REGSETALL)},
+	{1914,	0x0,		0x33f07ff,	(OFFSET_SEL | REGSETALL)},
+	{1915,	0x0,		0xc3c37ff,	(OFFSET_SEL | REGSETALL)},
+	{1916,	0x0,		0x1fffff10,	(OFFSET_SEL | REGSETALL)},
+	{1917,	0x0,		0x230070,	(OFFSET_SEL | REGSETALL)},
+	{1918,	0x0,		0x3ff7ffff,	(OFFSET_SEL | REG4G | REG2G | F_SET)},
+	{1918,	0x0,		0x3ff7ffff,	(OFFSET_SEL | REG8G | F_SET)},
+	{1919,	0x0,		0xe10,		(OFFSET_SEL | REGSETALL)},
+	{1920,	0x0,		0x1fffffff,	(OFFSET_SEL | REGSETALL)},
+	{1921,	0x0,		0x188411,	(OFFSET_SEL | REGSETALL)},
+	{1922,	0x0,		0x1fffffff,	(OFFSET_SEL | REGSETALL)},
+	{1923,	0x0,		0x180400,	(OFFSET_SEL | REGSETALL)},
+	{1924,	0x0,		0x1fffffff,	(OFFSET_SEL | REGSETALL)},
+	{1925,	0x0,		0x180400,	(OFFSET_SEL | REGSETALL)},
+	{1926,	0x0,		0x1fffffcf,	(OFFSET_SEL | REGSETALL)},
+	{1927,	0x0,		0x188400,	(OFFSET_SEL | REGSETALL)},
+	{1928,	0x0,		0x1fffffff,	(OFFSET_SEL | REGSETALL)},
+	{1929,	0x0,		0x4188411,	(OFFSET_SEL | REGSETALL)},
+	{1837,	0x0,		0x24410,	(OFFSET_SEL | REGSETALL)},
+	{1840,	0x0,		0x24410,	(OFFSET_SEL | REGSETALL)},
+	{1842,	0x0,		0x2ffff,	(OFFSET_SEL | REGSETALL)},
+	{76,	0xff0000f8,	0x00ff8f07,	(OFFSET_SEL | REGCLRSETALL)},
+	{332,	0xff0000f8,	0x00ff8f07,	(OFFSET_SEL | REGCLRSETALL)},
+	{588,	0xff0000f8,	0x00ff8f07,	(OFFSET_SEL | REGCLRSETALL)},
+	{844,	0xff0000f8,	0x00ff8f07,	(OFFSET_SEL | REGCLRSETALL)},
+	{77,	0xffff0000,	0xff8f,		(OFFSET_SEL | REGCLRSETALL)},
+	{333,	0xffff0000,	0xff8f,		(OFFSET_SEL | REGCLRSETALL)},
+	{589,	0xffff0000,	0xff8f,		(OFFSET_SEL | REGCLRSETALL)},
+	{845,	0xffff0000,	0xff8f,		(OFFSET_SEL | REGCLRSETALL)},
+	{1062,	0xffffff00,	0xff,		(OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
+	{1318,	0xffffff00,	0xff,		(OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
+	{1574,	0xffffff00,	0xff,		(OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
+	{1062,	0xffffff00,	0xfb,		(OFFSET_SEL | REG8G | F_CLRSET)},
+	{1318,	0xffffff00,	0xfb,		(OFFSET_SEL | REG8G | F_CLRSET)},
+	{1574,	0xffffff00,	0xfb,		(OFFSET_SEL | REG8G | F_CLRSET)},
+	{1028,	0xffffffff,	0x1000000,	(OFFSET_SEL | REGCLRSETALL)},
+	{1284,	0xffffffff,	0x1000000,	(OFFSET_SEL | REGCLRSETALL)},
+	{1540,	0xffffffff,	0x1000000,	(OFFSET_SEL | REGCLRSETALL)},
+	{1848,	0x0,		0x3cf07f8,	(OFFSET_SEL | REGSETALL)},
+	{1849,	0x0,		0x3f,		(OFFSET_SEL | REGSETALL)},
+	{1850,	0x0,		0x1fffff,	(OFFSET_SEL | REGSETALL)},
+	{1851,	0x0,		0x060000,	(OFFSET_SEL | REGSETALL)},
+	{130,	0x0000ffff,	0xffff0000,	(OFFSET_SEL | REGCLRSETALL)},
+	{386,	0x0000ffff,	0xffff0000,	(OFFSET_SEL | REGCLRSETALL)},
+	{642,	0x0000ffff,	0xffff0000,	(OFFSET_SEL | REGCLRSETALL)},
+	{898,	0x0000ffff,	0xffff0000,	(OFFSET_SEL | REGCLRSETALL)},
+	{131,	0xfffffff0,	0xf,		(OFFSET_SEL | REGCLRSETALL)},
+	{387,	0xfffffff0,	0xf,		(OFFSET_SEL | REGCLRSETALL)},
+	{643,	0xfffffff0,	0xf,		(OFFSET_SEL | REGCLRSETALL)},
+	{899,	0xfffffff0,	0xf,		(OFFSET_SEL | REGCLRSETALL)},
+	{29,	0xc0ffffff,	0x10000000,	(OFFSET_SEL | REGCLRSETALL)},
+	{285,	0xc0ffffff,	0x10000000,	(OFFSET_SEL | REGCLRSETALL)},
+	{541,	0xc0ffffff,	0x10000000,	(OFFSET_SEL | REGCLRSETALL)},
+	{797,	0xc0ffffff,	0x10000000,	(OFFSET_SEL | REGCLRSETALL)},
+	{30,	0xffffffff,	0x00080000,	(OFFSET_SEL | REGCLRSETALL)},
+	{286,	0xffffffff,	0x00080000,	(OFFSET_SEL | REGCLRSETALL)},
+	{542,	0xffffffff,	0x00080000,	(OFFSET_SEL | REGCLRSETALL)},
+	{798,	0xffffffff,	0x00080000,	(OFFSET_SEL | REGCLRSETALL)},
+	{31,	0xffffffc0,	0x00000010,	(OFFSET_SEL | REGCLRSETALL)},
+	{287,	0xffffffc0,	0x00000010,	(OFFSET_SEL | REGCLRSETALL)},
+	{543,	0xffffffc0,	0x00000010,	(OFFSET_SEL | REGCLRSETALL)},
+	{799,	0xffffffc0,	0x00000010,	(OFFSET_SEL | REGCLRSETALL)},
+	{1071,	0xfffffff0,	0x00000008,	(OFFSET_SEL | REGCLRSETALL)},
+	{1327,	0xfffffff0,	0x00000008,	(OFFSET_SEL | REGCLRSETALL)},
+	{1583,	0xfffffff0,	0x00000008,	(OFFSET_SEL | REGCLRSETALL)},
+	{1808,	0xfffffff0,	0x00000008,	(OFFSET_SEL | REGCLRSETALL)},
+	{1896,	0xfff0ffff,	0x00080000,	(OFFSET_SEL | REGCLRSETALL)},
 };
 
-void ddr_phy_start(u32 *phyreg, enum ddr_size_t size)
+void ddr_reg_set(u32 *reg, struct ddr_reg_cfg *data,
+		u32 len, u32 mask)
 {
-	u32 i, len;
-	u32 *addr, *reg;
-	u32 offset;
-
-	reg = phyreg + 4096;
+	u32 *addr;
+	u32 i;
 
-	len = sizeof(ddr_start_data)/sizeof(struct ddr_reg_clrset);
 	for (i = 0; i < len; i++) {
-
-		if ((size == DDR_SIZE_4G)  &&
-			(ddr_start_data[i].offset & DDR_2G_MASK))
+		if (!(data[i].flag & mask))
 			continue;
 
-		if (ddr_start_data[i].offset & OFFSET_SEL) {
-			offset = ddr_start_data[i].offset & (~OFFSET_SEL);
-			addr = reg;
-		} else {
-			offset = ddr_start_data[i].offset;
-			addr = phyreg + 2048;
-		}
-		offset &= (~DDR_2G_MASK);
-		DDR_REG_TRIGGER((addr + offset), ddr_start_data[i].mask,
-			ddr_start_data[i].val);
-	}
+		if (data[i].flag & OFFSET_SEL)
+			addr = reg + PHY_AC_BASE_ADDR + data[i].offset;
+		else
+			addr = reg + PHY_BASE_ADDR + data[i].offset;
 
-	out_le32(reg + 96, in_le32(reg + 96) + 0x300);
-	out_le32(reg + 352, in_le32(reg + 352) + 0x300);
-	out_le32(reg + 608, in_le32(reg + 608) + 0x300);
-	out_le32(reg + 864, in_le32(reg + 864) + 0x300);
+		if (data[i].flag & F_CLRSET)
+			DDR_REG_TRIGGER(addr, data[i].mask, data[i].val);
+		else if (data[i].flag & F_SET)
+			out_le32(addr, data[i].val);
+		else
+			out_le32(addr, in_le32(addr) + data[i].val);
+	}
+}
 
-	len = sizeof(ddr_start_data1)/sizeof(struct ddr_reg_clrset);
-	for (i = 0; i < len; i++)
-		DDR_REG_TRIGGER((reg + ddr_start_data1[i].offset),
-			ddr_start_data1[i].mask,
-			ddr_start_data1[i].val);
+void ddr_phy_start(u32 *phyreg, enum ddr_size_t size)
+{
+	u32 len;
+	u32 mask;
 
-	len = sizeof(ddr_start_data2)/sizeof(struct ddr_reg_set);
-	for (i = 0; i < len; i++)
-		out_le32((reg + ddr_start_data2[i].offset),
-			ddr_start_data2[i].val);
+	switch (size) {
+	case DDR_SIZE_2G:
+		mask = REG2G;
+		break;
 
-	len = sizeof(ddr_start_data3)/sizeof(struct ddr_reg_clrset);
-	for (i = 0; i < len; i++)
-		DDR_REG_TRIGGER((reg + ddr_start_data3[i].offset),
-			ddr_start_data3[i].mask,
-			ddr_start_data3[i].val);
+	case DDR_SIZE_4G:
+		mask = REG4G;
+		break;
 
-	out_le32((reg + 1848), 0x3cf07f8);
-	out_le32((reg + 1849), 0x3f);
-	out_le32((reg + 1850), 0x1fffff);
-	out_le32((reg + 1851), 0x060000);
+	case DDR_SIZE_8G:
+		mask = REG8G;
+		break;
 
-	len = sizeof(ddr_start_data4)/sizeof(struct ddr_reg_clrset);
-	for (i = 0; i < len; i++)
-		DDR_REG_TRIGGER((reg + ddr_start_data4[i].offset),
-			ddr_start_data4[i].mask,
-			ddr_start_data4[i].val);
+	case DDR_SIZE_16G:
+	default:
+		return;
+	};
 
+	len = sizeof(ddr_start_cfg) / sizeof(struct ddr_reg_cfg);
+	ddr_reg_set(phyreg, ddr_start_cfg, len, mask);
 	out_le32(phyreg, 0x01);
 }
-
diff --git a/drivers/ram/starfive/starfive_ddr.c b/drivers/ram/starfive/starfive_ddr.c
index 5865b43e6e..862a834a0c 100644
--- a/drivers/ram/starfive/starfive_ddr.c
+++ b/drivers/ram/starfive/starfive_ddr.c
@@ -11,6 +11,7 @@
 #include <fdtdec.h>
 #include <init.h>
 #include <ram.h>
+#include <reset.h>
 #include <syscon.h>
 #include <asm/io.h>
 #include <clk.h>
@@ -26,31 +27,12 @@ struct starfive_ddr_priv {
 	struct ram_info info;
 	void __iomem	*ctrlreg;
 	void __iomem	*phyreg;
+	struct reset_ctl rst_axi;
+	struct reset_ctl rst_osc;
+	struct reset_ctl rst_apb;
 	u32	fre;
 };
 
-static void ddr_assert_rst(ulong addr, ulong addr_status,
-			u32 mask)
-{
-	uint32_t tmp;
-
-	out_le32(addr, in_le32(addr) | mask);
-	do {
-		tmp = in_le32(addr_status);
-	} while ((tmp & mask) != 0);
-}
-
-static void ddr_clear_rst(ulong addr, ulong addr_status,
-			u32 mask)
-{
-	uint32_t tmp;
-
-	out_le32(addr, in_le32(addr) & (~mask));
-	do {
-		tmp = in_le32(addr_status);
-	} while ((tmp & mask) != mask);
-}
-
 static int starfive_ddr_setup(struct udevice *dev, struct starfive_ddr_priv *priv)
 {
 	enum ddr_size_t size;
@@ -63,18 +45,20 @@ static int starfive_ddr_setup(struct udevice *dev, struct starfive_ddr_priv *pri
 		size = DDR_SIZE_4G;
 		break;
 	case 0x200000000:
+		size = DDR_SIZE_8G;
+		break;
 	case 0x400000000:
 	default:
 		pr_err("unsupport size %lx\n", priv->info.size);
 		return -1;
 	}
-	ddr_phy_train(priv->phyreg + (2048 << 2));
-	ddr_phy_util(priv->phyreg + (4096 << 2));
-	ddr_phy_start(priv->phyreg, size);
 
-	clrsetbits_le32(CLK_DDR_BUS_REG, CLK_DDR_BUS_MASK, 0<<24);
+	ddr_phy_train(priv->phyreg + (PHY_BASE_ADDR << 2));
+	ddr_phy_util(priv->phyreg + (PHY_AC_BASE_ADDR << 2));
+	ddr_phy_start(priv->phyreg, size);
 
-	ddrcsr_boot(priv->ctrlreg, priv->ctrlreg + 0x1000,
+	DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
+	ddrcsr_boot(priv->ctrlreg, priv->ctrlreg + SEC_CTRL_ADDR,
 		   priv->phyreg, size);
 
 	return 0;
@@ -84,6 +68,7 @@ static int starfive_ddr_probe(struct udevice *dev)
 {
 	struct starfive_ddr_priv *priv = dev_get_priv(dev);
 	fdt_addr_t addr;
+	u64 rate;
 	int ret;
 
 	priv->dev = dev;
@@ -92,10 +77,21 @@ static int starfive_ddr_probe(struct udevice *dev)
 	addr = dev_read_addr_index(dev, 1);
 	priv->phyreg = (void __iomem *)addr;
 	ret = dev_read_u32(dev, "clock-frequency", &priv->fre);
-	if (ret) {
-		pr_err("clock-frequency not found in dt %d\n", ret);
-		return ret;
-	}
+	if (ret)
+		goto init_end;
+
+	ret = reset_get_by_name(dev, "axi", &priv->rst_axi);
+	if (ret)
+		goto init_end;
+
+	ret = reset_get_by_name(dev, "osc", &priv->rst_osc);
+	if (ret)
+		goto err_axi;
+
+	ret = reset_get_by_name(dev, "apb", &priv->rst_apb);
+	if (ret)
+		goto err_osc;
+
 	/* Read memory base and size from DT */
 	fdtdec_setup_mem_size_base();
 	priv->info.base = gd->ram_base;
@@ -103,58 +99,38 @@ static int starfive_ddr_probe(struct udevice *dev)
 
 	switch (priv->fre) {
 	case 2133:
-		clrsetbits_le32(CLK_DDR_BUS_REG, CLK_DDR_BUS_MASK, 0<<24);
-
-		starfive_jh7110_pll_set_rate(PLL1, 1066000000);
-
-		udelay(100);
-		clrsetbits_le32(CLK_DDR_BUS_REG, CLK_DDR_BUS_MASK, (1<<24)&CLK_DDR_BUS_MASK);
-
-		ddr_assert_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG,
-				RSTN_OSC_MASK);
-		ddr_clear_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG,
-				RSTN_OSC_MASK);
-		ddr_assert_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG,
-				RSTN_APB_MASK);
-		ddr_clear_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG,
-				RSTN_APB_MASK);
-		clrsetbits_le32(CLK_AXI_CTRL_REG, CLK_AXI_EN_MASK, (0<<31)&CLK_AXI_EN_MASK);
-
-		ddr_assert_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG,
-				RSTN_AXI_MASK);
-		ddr_clear_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG,
-				RSTN_AXI_MASK);
-
-		clrsetbits_le32(CLK_AXI_CTRL_REG, CLK_AXI_EN_MASK, (1<<31)&CLK_AXI_EN_MASK);
+		rate = 1066000000;
 		break;
 
 	case 2800:
-		clrsetbits_le32(CLK_DDR_BUS_REG, CLK_DDR_BUS_MASK, 0<<24);
-
-		starfive_jh7110_pll_set_rate(PLL1, 1400000000);
-
-		clrsetbits_le32(CLK_DDR_BUS_REG, CLK_DDR_BUS_MASK, 1<<24);
-
-		ddr_assert_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG,
-				RSTN_OSC_MASK);
-		ddr_clear_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG,
-				RSTN_OSC_MASK);
-		ddr_assert_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG,
-				RSTN_APB_MASK);
-		ddr_clear_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG,
-				RSTN_APB_MASK);
-		ddr_assert_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG,
-				RSTN_AXI_MASK);
-		ddr_clear_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG,
-				RSTN_AXI_MASK);
+		rate = 1400000000;
 		break;
 	default:
 		printk("Unknown DDR frequency %d\n", priv->fre);
-		break;
+		ret = -1;
+		goto init_end;
 	};
 
+	DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
+	starfive_jh7110_pll_set_rate(PLL1, rate);
+	udelay(100);
+	DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV2);
+	reset_assert(&priv->rst_osc);
+	reset_deassert(&priv->rst_osc);
+	reset_assert(&priv->rst_apb);
+	reset_deassert(&priv->rst_apb);
+	reset_assert(&priv->rst_axi);
+	reset_deassert(&priv->rst_axi);
+
 	ret = starfive_ddr_setup(dev, priv);
-	printf("DDR version: 600a6366.\n");
+	printf("DDR version: dc2e84f0.\n");
+		goto init_end;
+err_osc:
+	reset_free(&priv->rst_osc);
+err_axi:
+	reset_free(&priv->rst_axi);
+	pr_err("reset_get_by_name(axi) failed: %d", ret);
+init_end:
 
 	return ret;
 }
@@ -173,7 +149,7 @@ static struct ram_ops starfive_ddr_ops = {
 };
 
 static const struct udevice_id starfive_ddr_ids[] = {
-	{ .compatible = "starfive,jh7110-ddr" },
+	{ .compatible = "starfive,jh7110-dmc" },
 	{ }
 };
 
diff --git a/drivers/ram/starfive/starfive_ddr.h b/drivers/ram/starfive/starfive_ddr.h
index 00bd89339f..4877489079 100644
--- a/drivers/ram/starfive/starfive_ddr.h
+++ b/drivers/ram/starfive/starfive_ddr.h
@@ -8,42 +8,41 @@
 #ifndef __STARFIVE_DDR_H__
 #define __STARFIVE_DDR_H__
 
-#include <common.h>
-#include <asm/io.h>
-#include <inttypes.h>
+#define JH7110_SYS_CRG	0x13020000
 
-#define SYS_CRG_BASE		0x13020000
-#define SYS_SYSCON_BASE		0x13030000
+#define SEC_CTRL_ADDR		0x1000
+#define PHY_BASE_ADDR		0x800
+#define PHY_AC_BASE_ADDR	0x1000
 
-#define CLK_DDR_BUS_REG		(SYS_CRG_BASE + 0xAC)
-#define CLK_AXI_CTRL_REG	(SYS_CRG_BASE + 0xB0)
+#define DDR_BUS_MASK		GENMASK(29, 24)
+#define DDR_AXI_MASK		BIT(31)
+#define DDR_BUS_OFFSET		0xAC
+#define DDR_AXI_OFFSET		0xB0
 
-#define RESET_ASSERT0_REG	(SYS_CRG_BASE + 0x2F8)
-#define RESET_ASSERT1_REG	(SYS_CRG_BASE + 0x2FC)
-#define RESET_ASSERT2_REG	(SYS_CRG_BASE + 0x300)
-#define RESET_ASSERT3_REG	(SYS_CRG_BASE + 0x304)
+#define DDR_BUS_OSC_DIV2	0
+#define DDR_BUS_PLL1_DIV2	1
+#define DDR_BUS_PLL1_DIV4	2
+#define DDR_BUS_PLL1_DIV8	3
+#define DDR_AXI_DISABLE		0
+#define DDR_AXI_ENABLE		1
 
-#define RESET_STATUS0_REG	(SYS_CRG_BASE + 0x308)
-#define RESET_STATUS1_REG	(SYS_CRG_BASE + 0x30C)
-#define RESET_STATUS2_REG	(SYS_CRG_BASE + 0x310)
-#define RESET_STATUS3_REG	(SYS_CRG_BASE + 0x314)
+#define OFFSET_SEL		BIT(31)
+#define REG2G			BIT(30)
+#define REG4G			BIT(29)
+#define REG8G			BIT(28)
+#define F_ADDSET		BIT(2)
+#define F_SET			BIT(1)
+#define F_CLRSET		BIT(0)
+#define REGALL			(REG2G | REG4G | REG8G)
+#define REGSETALL		(F_SET | REGALL)
+#define REGCLRSETALL		(F_CLRSET | REGALL)
+#define REGADDSETALL		(F_ADDSET | REGALL)
 
-#define RSTN_AXI_MASK		(0x1 << 6)
-#define RSTN_OSC_MASK		(0x1 << 7)
-#define RSTN_APB_MASK		(0x1 << 8)
-
-#define CLK_DDR_BUS_MASK    	0x3000000U
-#define CLK_AXI_EN_MASK		0x80000000U
-
-struct ddr_reg_set{
-	u32 offset;
-	u32 val;
-};
-
-struct ddr_reg_clrset{
+struct ddr_reg_cfg {
 	u32 offset;
 	u32 mask;
 	u32 val;
+	u32 flag;
 };
 
 enum ddr_size_t {
@@ -61,5 +60,10 @@ void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size);
 #define DDR_REG_TRIGGER(addr, mask, value) \
 	out_le32((addr), (in_le32(addr) & (mask)) | (value))
 
+#define DDR_REG_SET(type, val) \
+	clrsetbits_le32(JH7110_SYS_CRG + DDR_##type##_OFFSET, \
+		DDR_##type##_MASK, \
+		((val) << __ffs(DDR_##type##_MASK)) & DDR_##type##_MASK)
+
 #endif /*__STARFIVE_DDR_H__*/