diff options
author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-05-15 09:03:29 +0300 |
---|---|---|
committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:35 +0300 |
commit | b8ceeb8238c4db755c2a3e5fe178568bd2d4c568 (patch) | |
tree | 7c15fe84f58b6c454f31930f98ac409d84936529 /drivers/ram | |
parent | db61964dc2ecbbc9fb7fb89f0eed597b4429c82f (diff) | |
download | u-boot-b8ceeb8238c4db755c2a3e5fe178568bd2d4c568.tar.xz |
ram:starfive: add ddr driver
Add driver for JH7110 to support ddr initialization in SPL.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
Signed-off-by: samin <samin.guo@starfivetech.com>
Diffstat (limited to 'drivers/ram')
-rw-r--r-- | drivers/ram/Kconfig | 1 | ||||
-rw-r--r-- | drivers/ram/Makefile | 3 | ||||
-rw-r--r-- | drivers/ram/starfive/Kconfig | 21 | ||||
-rw-r--r-- | drivers/ram/starfive/Makefile | 11 | ||||
-rw-r--r-- | drivers/ram/starfive/ddrcsr_boot.c | 276 | ||||
-rw-r--r-- | drivers/ram/starfive/ddrphy_start.c | 299 | ||||
-rw-r--r-- | drivers/ram/starfive/ddrphy_train.c | 385 | ||||
-rw-r--r-- | drivers/ram/starfive/ddrphy_utils.c | 1957 | ||||
-rw-r--r-- | drivers/ram/starfive/starfive_ddr.c | 181 | ||||
-rw-r--r-- | drivers/ram/starfive/starfive_ddr.h | 69 |
10 files changed, 3203 insertions, 0 deletions
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index a79594d351..e9845e008b 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -100,3 +100,4 @@ source "drivers/ram/rockchip/Kconfig" source "drivers/ram/sifive/Kconfig" source "drivers/ram/stm32mp1/Kconfig" source "drivers/ram/octeon/Kconfig" +source "drivers/ram/starfive/Kconfig" diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 5a39611349..f4c48a4ae6 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -22,3 +22,6 @@ obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o obj-$(CONFIG_RAM_SIFIVE) += sifive/ obj-$(CONFIG_ARCH_OCTEON) += octeon/ +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/ +endif
\ No newline at end of file diff --git a/drivers/ram/starfive/Kconfig b/drivers/ram/starfive/Kconfig new file mode 100644 index 0000000000..b4e269a650 --- /dev/null +++ b/drivers/ram/starfive/Kconfig @@ -0,0 +1,21 @@ +config SPL_STARFIVE_DDR + bool "STARFive DDR driver in SPL" + depends on SPL_RAM && STARFIVE_JH7110 + help + This enables DDR support for the platforms based on StarFive SoC. + +choice + prompt "DDR working frequency" + depends on SPL_STARFIVE_DDR + default STARFIVE_DDR_2133 + help + choice DDR working frequency(Default is 2133M). + + config STARFIVE_DDR_2133 + bool "Frequency of DDR is 2133M" + config STARFIVE_DDR_2800 + bool "Frequency of DDR is 2800M" + config STARFIVE_DDR_3200 + bool "Frequency of DDR is 3200M" + +endchoice diff --git a/drivers/ram/starfive/Makefile b/drivers/ram/starfive/Makefile new file mode 100644 index 0000000000..1df42c377b --- /dev/null +++ b/drivers/ram/starfive/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2022 StarFive, Inc +# +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_start.o +obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_train.o +obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive_ddr.o +obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_utils.o +obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrcsr_boot.o +endif
\ No newline at end of file diff --git a/drivers/ram/starfive/ddrcsr_boot.c b/drivers/ram/starfive/ddrcsr_boot.c new file mode 100644 index 0000000000..bc4b49fd35 --- /dev/null +++ b/drivers/ram/starfive/ddrcsr_boot.c @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong <yanhong.wang@starfivetech.com> + * + */ + +#include "starfive_ddr.h" +#include <linux/delay.h> + +#define DDRSEC_SEL 0x80000000 +#define REGOFFSET(offset) ((offset) / 4) + +static struct ddr_reg_set ddr_cfg[] = { + {0x0, 0x00000001}, + {(DDRSEC_SEL | 0xf00), 0x40001030}, + {(DDRSEC_SEL | 0xf04), 0x00000001}, + {(DDRSEC_SEL | 0xf10), 0x00400000}, + {(DDRSEC_SEL | 0xf14), 0x043fffff}, + {(DDRSEC_SEL | 0xf18), 0x00000000}, + {(DDRSEC_SEL | 0xf30), 0x1f000041}, + {(DDRSEC_SEL | 0xf34), 0x1f000041}, + {(DDRSEC_SEL | 0x110), 0xc0000001}, + {(DDRSEC_SEL | 0x114), 0xffffffff}, + {0x10c, 0x00000505}, + {0x11c, 0x00000000}, + {0x500, 0x00000201}, + {0x514, 0x00000100}, + {0x6a8, 0x00040000}, + {0xea8, 0x00040000}, + {0x504, 0x40000000} +}; + +static struct ddr_reg_set ddr_cfg1[] = { + {0x310, 0x00020000}, + {0x310, 0x00020001}, + {0x600, 0x002e0176}, + {0x604, 0x002e0176}, + {0x608, 0x001700bb}, + {0x60c, 0x000b005d}, + {0x610, 0x0005002e}, + {0x614, 0x00020017}, + {0x618, 0x00020017}, + {0x61c, 0x00020017}, + {0x678, 0x00000019}, + {0x100, 0x000000f8}, + {0x620, 0x03030404}, + {0x624, 0x04030505}, + {0x628, 0x07030884}, + {0x62c, 0x13150401}, + {0x630, 0x17150604}, + {0x634, 0x00110000}, + {0x638, 0x200a0a08}, + {0x63c, 0x1730f803}, + {0x640, 0x000a0c00}, + {0x644, 0xa005000a}, + {0x648, 0x00000000}, + {0x64c, 0x00081306}, + {0x650, 0x04070304}, + {0x654, 0x00000404}, + {0x658, 0x00000060}, + {0x65c, 0x00030008}, + {0x660, 0x00000000}, + {0x680, 0x00000603}, + {0x684, 0x01000202}, + {0x688, 0x0413040d}, + {0x68c, 0x20002420}, + {0x690, 0x00140000}, + {0x69c, 0x01240074}, + {0x6a0, 0x00000000}, + {0x6a4, 0x20240c00}, + {0x6a8, 0x00040000}, + {0x4, 0x30010006}, + {0xc, 0x00000002}, + {0x4, 0x30020000}, + {0xc, 0x00000002}, + {0x4, 0x30030031}, + {0xc, 0x00000002}, + {0x4, 0x300b0033}, + {0xc, 0x00000002}, + {0x4, 0x30160016}, + {0xc, 0x00000002}, + {0x10, 0x00000010}, + {0x14, 0x00000001}, +}; + +static struct ddr_reg_clrset ddr_cfg2[] = { + {46, ~(0xF << 24), (0x3 << 24)}, + {33, ~(0x1 << 24), 0x0}, + {44, ~(0x1 << 16), 0x0}, + {44, ~(0x1 << 24), 0x0}, + {45, 0xffffffff, 0x1}, + {146, 0xffffffff, (0x3 << 24)}, + {147, 0xffffffff, (0x3 << 8)}, + {147, 0xffffffff, (0x3 << 24)}, + {44, 0xffffffff, (0x1 << 8)}, + {46, ~(0xF << 16), (0x3 << 16)}, + {33, ~(0x1 << 16), 0x0}, + {43, ~(0x1 << 16), 0x0}, + {43, ~(0x1 << 24), 0x0}, + {44, 0xffffffff, 0x1}, + {146, 0xffffffff, (0x3 << 16)}, + {147, 0xffffffff, 0x3}, + {147, 0xffffffff, (0x3 << 16)}, + {148, 0xffffffff, (0x3 << 24)}, + {149, 0xffffffff, (0x3 << 24)}, + {150, 0xffffffff, (0x3 << 24)}, + {43, 0xffffffff, (0x1 << 8)}, + {67, ~(0xF << 8), (0x3 << 8)}, + {68, ~(0x1 << 8), 0x0}, + {71, ~(0x1 << 16), 0x0}, + {71, ~(0x1 << 24), 0x0}, + {72, 0xffffffff, (0x1 << 8)}, + {180, 0xffffffff, (0x3 << 8)}, + {183, 0xffffffff, (0x3 << 8)}, + {186, 0xffffffff, (0x3 << 8)}, +}; + +static struct ddr_reg_set ddr_cfg3[] = { + {0x100, 0x000000e0}, + {0x620, 0x04041417}, + {0x624, 0x09110609}, + {0x628, 0x442d0994}, + {0x62c, 0x271e102b}, + {0x630, 0x291b140a}, + {0x634, 0x001c0000}, + {0x638, 0x200f0f08}, + {0x63c, 0x29420a06}, + {0x640, 0x019e1fc1}, + {0x644, 0x10cb0196}, + {0x648, 0x00000000}, + {0x64c, 0x00082714}, + {0x650, 0x16442f0d}, + {0x654, 0x00001916}, + {0x658, 0x00000060}, + {0x65c, 0x00600020}, + {0x660, 0x00000000}, + {0x680, 0x0c00040f}, + {0x684, 0x03000604}, + {0x688, 0x0515040d}, + {0x68c, 0x20002c20}, + {0x690, 0x00140000}, + {0x69c, 0x01240074}, + {0x6a0, 0x00000000}, + {0x6a4, 0x202c0c00}, + {0x6a8, 0x00040000}, + {0x4, 0x30010036}, + {0xc, 0x00000002}, + {0x4, 0x3002001b}, + {0xc, 0x00000002}, + {0x4, 0x30030031}, + {0xc, 0x00000002}, + {0x4, 0x300b0066}, + {0xc, 0x00000002}, + {0x4, 0x30160016}, + {0xc, 0x00000002}, + {0x410, 0x00101010}, + {0x420, 0x0c181006}, + {0x424, 0x20200820}, + {0x428, 0x80000020}, + {0x0, 0x00000001}, + {0x108, 0x00003000}, + {DDRSEC_SEL | 0x704, 0x00000007}, + {0x330, 0x09313fff}, + {0x508, 0x00000033}, + {0x324, 0x00002000}, + {0x104, 0x90000000}, + {0x510, 0x00000100}, + {0x514, 0x00000000}, + {DDRSEC_SEL | 0x700, 0x00000003}, + {0x514, 0x00000600}, + {0x20, 0x00000001}, +}; + +void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg) +{ + u32 i, len; + u32 *addr; + u32 val; + + len = sizeof(ddr_cfg)/sizeof(struct ddr_reg_set); + for (i = 0; i < len; i++) { + if (ddr_cfg[i].offset & DDRSEC_SEL) + addr = secreg + REGOFFSET(ddr_cfg[i].offset & (~DDRSEC_SEL)); + else + addr = csrreg + REGOFFSET(ddr_cfg[i].offset); + out_le32(addr, ddr_cfg[i].val); + } + + do { + udelay(1); + val = in_le32(csrreg + REGOFFSET(0x504)); + } while ((val & 0x80000000) != 0x80000000); + + out_le32(csrreg + REGOFFSET(0x504), 0x00000000); + out_le32(csrreg + REGOFFSET(0x50c), 0x00000000); + udelay(300); + out_le32(csrreg + REGOFFSET(0x50c), 0x00000001); + udelay(3000); + out_le32(csrreg + REGOFFSET(0x10), 0x0000003c); + out_le32(csrreg + REGOFFSET(0x14), 0x00000001); + udelay(4); + + len = sizeof(ddr_cfg1) / sizeof(struct ddr_reg_set); + for (i = 0; i < len; i++) + out_le32(csrreg + REGOFFSET(ddr_cfg1[i].offset), ddr_cfg1[i].val); + + udelay(4); + out_le32(csrreg + REGOFFSET(0x10), 0x00000011); + out_le32(csrreg + REGOFFSET(0x14), 0x00000001); + out_le32(csrreg + REGOFFSET(0x10), 0x00000020); + out_le32(csrreg + REGOFFSET(0x14), 0x00000001); + + udelay(4); + out_le32(csrreg + REGOFFSET(0x10), 0x00000021); + out_le32(csrreg + REGOFFSET(0x14), 0x00000001); + out_le32(csrreg + REGOFFSET(0x514), 0x00000000); + + do { + udelay(1); + val = in_le32(csrreg + REGOFFSET(0x518)); + } while ((val & 0x2) != 0x2); + + val = in_le32(csrreg + REGOFFSET(0x518)); + while ((val & 0x2) != 0x0) { + val = in_le32(phyreg + 1); + if ((val & 0x20) == 0x20) { + switch (val & 0x0000001f) { + case 0: //ddrc_clock=12M + clrsetbits_le32(CLK_DDR_BUS_REG, + CLK_DDR_BUS_MASK, 0<<24); + break; + case 1: //ddrc_clock=200M + clrsetbits_le32(CLK_DDR_BUS_REG, + CLK_DDR_BUS_MASK, 3<<24); + break; + case 2: //ddrc_clock=800M + clrsetbits_le32(CLK_DDR_BUS_REG, + CLK_DDR_BUS_MASK, 1<<24); + break; + default: + break; + }; + + out_le32((phyreg + 2), 0x1); + do { + udelay(2); + val = in_le32(phyreg + 2); + } while ((val & 0x00000001) != 0x00000000); + } + udelay(1); + val = in_le32(csrreg + REGOFFSET(0x518)); + }; + + val = in_le32(phyreg + 2048 + 83); + val = in_le32(phyreg + 2048 + 84); + out_le32((phyreg + 2048 + 84), val & 0xF8000000); + + len = sizeof(ddr_cfg2) / sizeof(struct ddr_reg_clrset); + for (i = 0; i < len; i++) { + addr = phyreg + 2048; + addr += ddr_cfg2[i].offset; + DDR_REG_TRIGGER(addr, ddr_cfg2[i].mask, ddr_cfg2[i].val); + } + + len = sizeof(ddr_cfg3)/sizeof(struct ddr_reg_set); + for (i = 0; i < len; i++) { + if (ddr_cfg3[i].offset & DDRSEC_SEL) + addr = secreg + REGOFFSET(ddr_cfg3[i].offset & (~DDRSEC_SEL)); + else + addr = csrreg + REGOFFSET(ddr_cfg3[i].offset); + + out_le32(addr, ddr_cfg3[i].val); + } +} + diff --git a/drivers/ram/starfive/ddrphy_start.c b/drivers/ram/starfive/ddrphy_start.c new file mode 100644 index 0000000000..41866c1fe6 --- /dev/null +++ b/drivers/ram/starfive/ddrphy_start.c @@ -0,0 +1,299 @@ + +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong <yanhong.wang@starfivetech.com> + * + */ + +#include "starfive_ddr.h" + +#define G_SPEED_2133 1 + +#define OFFSET_SEL 0x80000000 + +static struct ddr_reg_clrset ddr_start_data[] = { + {(OFFSET_SEL | 89), 0xffffff00, 0x00000051}, + {(OFFSET_SEL | 78), 0xfffffcff, 0x0}, + {(OFFSET_SEL | 345), 0xffffff00, 0x00000051}, + {(OFFSET_SEL | 334), 0xfffffcff, 0x0}, + {(OFFSET_SEL | 601), 0xffffff00, 0x00000051}, + {(OFFSET_SEL | 590), 0xfffffcff, 0x0}, + {(OFFSET_SEL | 857), 0xffffff00, 0x00000051}, + {(OFFSET_SEL | 846), 0xfffffcff, 0x0}, + {(OFFSET_SEL | 1793), 0xfffffeff, 0x0}, + {(OFFSET_SEL | 1793), 0xfffcffff, 0x0}, + {(OFFSET_SEL | 125), 0xfff0ffff, 0x00010000}, + {(OFFSET_SEL | 102), 0xfffffffc, 0x00000001}, + {(OFFSET_SEL | 105), 0xffffffe0, 0x00000001}, + {(OFFSET_SEL | 92), 0xfffffffe, 0x00000001}, + {(OFFSET_SEL | 94), 0xffffe0ff, 0x00000200}, + {(OFFSET_SEL | 96), 0xfffff0ff, 0x00000400}, + {(OFFSET_SEL | 89), 0xffffff00, 0x00000051}, + {(OFFSET_SEL | 381), 0xfff0ffff, 0x00010000}, + {(OFFSET_SEL | 358), 0xfffffffc, 0x00000001}, + {(OFFSET_SEL | 361), 0xffffffe0, 0x00000001}, + {(OFFSET_SEL | 348), 0xfffffffe, 0x00000001}, + {(OFFSET_SEL | 350), 0xffffe0ff, 0x00000200}, + {(OFFSET_SEL | 352), 0xfffff0ff, 0x00000400}, + {(OFFSET_SEL | 345), 0xffffff00, 0x00000051}, + {(OFFSET_SEL | 637), 0xfff0ffff, 0x00010000}, + {(OFFSET_SEL | 614), 0xfffffffc, 0x00000001}, + {(OFFSET_SEL | 617), 0xffffffe0, 0x00000001}, + {(OFFSET_SEL | 604), 0xfffffffe, 0x00000001}, + {(OFFSET_SEL | 606), 0xffffe0ff, 0x00000200}, + {(OFFSET_SEL | 608), 0xfffff0ff, 0x00000400}, + {(OFFSET_SEL | 601), 0xffffff00, 0x00000051}, + {(OFFSET_SEL | 893), 0xfff0ffff, 0x00010000}, + {(OFFSET_SEL | 870), 0xfffffffc, 0x00000001}, + {(OFFSET_SEL | 873), 0xffffffe0, 0x00000001}, + {(OFFSET_SEL | 860), 0xfffffffe, 0x00000001}, + {(OFFSET_SEL | 862), 0xffffe0ff, 0x00000200}, + {(OFFSET_SEL | 864), 0xfffff0ff, 0x00000400}, + {(OFFSET_SEL | 857), 0xffffff00, 0x00000051}, + {(OFFSET_SEL | 1895), 0xffffe000, 0x00001342}, + {(OFFSET_SEL | 1835), 0xfffff0ff, 0x00000200}, + {(OFFSET_SEL | 1793), 0xfffffeff, 0x00000100}, + {62, 0xfffffeff, 0x0}, + {66, 0xfffffeff, 0x0}, + {166, 0xffffff80, 0x00000001}, + {62, 0xfff0ffff, 0x00010000}, + {62, 0xf0ffffff, 0x01000000}, + {166, 0xffff80ff, 0x00000100}, + {179, 0xff80ffff, 0x00010000}, + {67, 0xffe0ffff, 0x00010000}, + {67, 0xe0ffffff, 0x01000000}, + {179, 0x80ffffff, 0x01000000}, + {166, 0xff80ffff, 0x00010000}, + {62, 0xfff0ffff, 0x00010000}, + {62, 0xf0ffffff, 0x01000000}, + {166, 0x80ffffff, 0x01000000}, + {182, 0xff80ffff, 0x00010000}, + {67, 0xffe0ffff, 0x00010000}, + {67, 0xe0ffffff, 0x01000000}, + {182, 0x80ffffff, 0x01000000}, + {167, 0xffffff80, 0x00000017}, + {62, 0xfff0ffff, 0x00010000}, + {62, 0xf0ffffff, 0x01000000}, + {167, 0xffff80ff, 0x00001700}, + {185, 0xff80ffff, 0x00200000}, + {67, 0xffe0ffff, 0x00010000}, + {67, 0xe0ffffff, 0x01000000}, + {185, 0x80ffffff, 0x20000000}, + {10, 0xffffffe0, 0x00000002}, + {0, 0xfffffffe, 0x00000001}, +#ifdef G_DDR_SIMULATION + {(OFFSET_SEL | 1860), 0x80ffffff, 0x01000000}, +#endif + {247, 0xffffffff, 0x00000008}, + {249, 0xffffffff, 0x00000800}, + {252, 0xffffffff, 0x00000008}, + {254, 0xffffffff, 0x00000800}, + {281, 0xffffffff, 0x33000000}, + {305, 0xffffffff, 0x33000000}, + {329, 0xffffffff, 0x33000000}, + {353, 0xffffffff, 0x33000000}, + {289, 0xffffffff, 0x66000000}, + {313, 0xffffffff, 0x66000000}, + {337, 0xffffffff, 0x66000000}, + {361, 0xffffffff, 0x66000000}, + {282, 0xffffffff, 0x00160000}, + {306, 0xffffffff, 0x00160000}, + {330, 0xffffffff, 0x00160000}, + {354, 0xffffffff, 0x00160000}, + {290, 0xffffffff, 0x00160000}, + {314, 0xffffffff, 0x00160000}, + {338, 0xffffffff, 0x00160000}, + {362, 0xffffffff, 0x00160000}, + {282, 0xffffff00, 0x17}, + {306, 0xffffff00, 0x17}, + {330, 0xffffff00, 0x17}, + {354, 0xffffff00, 0x17}, + {290, 0xffffff00, 0x17}, + {314, 0xffffff00, 0x17}, + {338, 0xffffff00, 0x17}, + {362, 0xffffff00, 0x17}, + {282, 0xffff00ff, 0x2000}, + {306, 0xffff00ff, 0x2000}, + {330, 0xffff00ff, 0x2000}, + {354, 0xffff00ff, 0x2000}, + {290, 0xffff00ff, 0x2000}, + {314, 0xffff00ff, 0x2000}, + {338, 0xffff00ff, 0x2000}, + {362, 0xffff00ff, 0x2000}, + {(OFFSET_SEL | 65), 0xffffffff, 0x00000100}, + {(OFFSET_SEL | 321), 0xffffffff, 0x00000100}, + {(OFFSET_SEL | 577), 0xffffffff, 0x00000100}, + {(OFFSET_SEL | 833), 0xffffffff, 0x00000100}, +}; + +static struct ddr_reg_clrset ddr_start_data1[] = { +#ifdef G_SPEED_3200 + {96, 0xff00ffff, 0x00180000}, + {352, 0xff00ffff, 0x00180000}, + {608, 0xff00ffff, 0x00180000}, + {864, 0xff00ffff, 0x00180000}, +#elif defined G_SPEED_2666 + {96, 0xff00ffff, 0x00140000}, + {352, 0xff00ffff, 0x00140000}, + {608, 0xff00ffff, 0x00140000}, + {864, 0xff00ffff, 0x00140000}, +#elif defined G_SPEED_2133 + {96, 0xff00ffff, 0x00120000}, + {352, 0xff00ffff, 0x00120000}, + {608, 0xff00ffff, 0x00120000}, + {864, 0xff00ffff, 0x00120000}, +#endif + {33, 0xffffff00, 0x0040}, + {289, 0xffffff00, 0x0040}, + {545, 0xffffff00, 0x0040}, + {801, 0xffffff00, 0x0040}, + {1038, 0xfcffffff, 0x03000000}, + {1294, 0xfcffffff, 0x03000000}, + {1550, 0xfcffffff, 0x03000000}, + {83, 0xffc0ffff, 0x70000}, + {339, 0xffc0ffff, 0x70000}, + {595, 0xffc0ffff, 0x70000}, + {851, 0xffc0ffff, 0x70000}, + {1062, 0xf800ffff, 0x70000}, + {1318, 0xf800ffff, 0x70000}, + {1574, 0xf800ffff, 0x70000}, + {1892, 0xfffc0000, 0x15547}, + {1893, 0xfffc0000, 0x7}, + {1852, 0xffffe000, 0x07a}, + {1853, 0xffffffff, 0x0100}, + {1822, 0xffffffff, 0xFF}, + {1896, 0xfffffc00, 0x03d5}, + {91, 0xfc00ffff, 0x03d50000}, + {347, 0xfc00ffff, 0x03d50000}, + {603, 0xfc00ffff, 0x03d50000}, + {859, 0xfc00ffff, 0x03d50000}, +}; + +static struct ddr_reg_set ddr_start_data2[] = { + + {1912, 0xcc3bfc7}, + {1913, 0xff8f}, + {1914, 0x33f07ff}, + {1915, 0xc3c37ff}, + {1916, 0x1fffff10}, + {1917, 0x230070}, + {1918, 0x3ff7ffff}, + {1919, 0xe10}, + {1920, 0x1fffffff}, + {1921, 0x188411}, + {1922, 0x1fffffff}, + {1923, 0x180400}, + {1924, 0x1fffffff}, + {1925, 0x180400}, + {1926, 0x1fffffcf}, + {1927, 0x188400}, + {1928, 0x1fffffff}, + {1929, 0x4188411}, + {1837, 0x24410}, + {1840, 0x24410}, + {1842, 0x2ffff}, +}; + +static struct ddr_reg_clrset ddr_start_data3[] = { + {76, 0xff0000f8, 0x00ff8f07}, + {332, 0xff0000f8, 0x00ff8f07}, + {588, 0xff0000f8, 0x00ff8f07}, + {844, 0xff0000f8, 0x00ff8f07}, + {77, 0xffff0000, 0xff8f}, + {333, 0xffff0000, 0xff8f}, + {589, 0xffff0000, 0xff8f}, + {845, 0xffff0000, 0xff8f}, + {1062, 0xffffff00, 0xff}, + {1318, 0xffffff00, 0xff}, + {1574, 0xffffff00, 0xff}, + {1028, 0xffffffff, 0x1000000}, + {1284, 0xffffffff, 0x1000000}, + {1540, 0xffffffff, 0x1000000}, +}; + +static struct ddr_reg_clrset ddr_start_data4[] = { + {130, 0x0000ffff, 0xffff0000}, + {386, 0x0000ffff, 0xffff0000}, + {642, 0x0000ffff, 0xffff0000}, + {898, 0x0000ffff, 0xffff0000}, + {131, 0xfffffff0, 0xf}, + {387, 0xfffffff0, 0xf}, + {643, 0xfffffff0, 0xf}, + {899, 0xfffffff0, 0xf}, + {29, 0xc0ffffff, 0x10000000}, + {285, 0xc0ffffff, 0x10000000}, + {541, 0xc0ffffff, 0x10000000}, + {797, 0xc0ffffff, 0x10000000}, + {30, 0xffffffff, 0x00080000}, + {286, 0xffffffff, 0x00080000}, + {542, 0xffffffff, 0x00080000}, + {798, 0xffffffff, 0x00080000}, + {31, 0xffffffc0, 0x00000010}, + {287, 0xffffffc0, 0x00000010}, + {543, 0xffffffc0, 0x00000010}, + {799, 0xffffffc0, 0x00000010}, + {1071, 0xfffffff0, 0x00000008}, + {1327, 0xfffffff0, 0x00000008}, + {1583, 0xfffffff0, 0x00000008}, + {1808, 0xfffffff0, 0x00000008}, + {1896, 0xfff0ffff, 0x00080000}, +}; + +void ddr_phy_start(u32 *phyreg) +{ + u32 i, len; + u32 *addr, *reg; + u32 offset; + + reg = phyreg + 4096; + + len = sizeof(ddr_start_data)/sizeof(struct ddr_reg_clrset); + for (i = 0; i < len; i++) { + if (ddr_start_data[i].offset & OFFSET_SEL) { + offset = ddr_start_data[i].offset & (~OFFSET_SEL); + addr = reg; + } else { + offset = ddr_start_data[i].offset; + addr = phyreg + 2048; + } + DDR_REG_TRIGGER((addr + offset), ddr_start_data[i].mask, + ddr_start_data[i].val); + } + + out_le32(reg + 96, in_le32(reg + 96) + 0x300); + out_le32(reg + 352, in_le32(reg + 352) + 0x300); + out_le32(reg + 608, in_le32(reg + 608) + 0x300); + out_le32(reg + 864, in_le32(reg + 864) + 0x300); + + len = sizeof(ddr_start_data1)/sizeof(struct ddr_reg_clrset); + for (i = 0; i < len; i++) + DDR_REG_TRIGGER((reg + ddr_start_data1[i].offset), + ddr_start_data1[i].mask, + ddr_start_data1[i].val); + + len = sizeof(ddr_start_data2)/sizeof(struct ddr_reg_set); + for (i = 0; i < len; i++) + out_le32((reg + ddr_start_data2[i].offset), + ddr_start_data2[i].val); + + len = sizeof(ddr_start_data3)/sizeof(struct ddr_reg_clrset); + for (i = 0; i < len; i++) + DDR_REG_TRIGGER((reg + ddr_start_data3[i].offset), + ddr_start_data3[i].mask, + ddr_start_data3[i].val); + + out_le32((reg + 1848), 0x3cf07f8); + out_le32((reg + 1849), 0x3f); + out_le32((reg + 1850), 0x1fffff); + out_le32((reg + 1851), 0x060000); + + len = sizeof(ddr_start_data4)/sizeof(struct ddr_reg_clrset); + for (i = 0; i < len; i++) + DDR_REG_TRIGGER((reg + ddr_start_data4[i].offset), + ddr_start_data4[i].mask, + ddr_start_data4[i].val); + + out_le32(phyreg, 0x01); +} + diff --git a/drivers/ram/starfive/ddrphy_train.c b/drivers/ram/starfive/ddrphy_train.c new file mode 100644 index 0000000000..d5888c9413 --- /dev/null +++ b/drivers/ram/starfive/ddrphy_train.c @@ -0,0 +1,385 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong <yanhong.wang@starfivetech.com> + * + */ + +#include <common.h> +#include <asm/io.h> + +static u32 ddr_train_data[] = { + 0xb00, + 0x101, + 0x640000, + 0x1, + 0x0, + 0x0, + 0x0, + 0x0, + 0x1, + 0x7, + 0x10002, + 0x300080f, + 0x1, + 0x5, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x1010000, + 0x280a0000, + 0x0, + 0x1, + 0x3200000f, + 0x0, + 0x0, + 0x10102, + 0x1, + 0x0, + 0x0, + 0x0, + 0xaa, + 0x55, + 0xb5, + 0x4a, + 0x56, + 0xa9, + 0xa9, + 0xb5, + 0x1000000, + 0x1000000, + 0x0, + 0xf0f0000, + 0x14, + 0x7d0, + 0x300, + 0x0, + 0x0, + 0x1000000, + 0x10101, + 0x0, + 0x30000, + 0x100, + 0x170f, + 0x0, + 0x0, + 0x0, + 0xa140a01, + 0x204010a, + 0x2080510, + 0x40400, + 0x1000101, + 0x10100, + 0x2040f00, + 0x34000000, + 0x0, + 0x0, + 0x1000000, + 0x0, + 0x0, + 0x0, + 0x0, + 0x10100, + 0x80101, + 0x2000200, + 0x1000100, + 0x1000000, + 0x2000200, + 0x200, + 0x0, + 0x0, + 0x0, + 0xe000004, + 0xc0d100f, + 0xa09080b, + 0x2010000, + 0x80103, + 0x200, + 0x0, + 0xf000000, + 0x4, + 0xa, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x30100, + 0x1010001, + 0x10200, + 0x4000103, + 0x1050001, + 0x10600, + 0x107, + 0x0, + 0x0, + 0x10001, + 0x0, + 0x0, + 0x0, + 0x0, + 0x10000, + 0x4, + 0x0, + 0x10000, + 0x0, + 0x3c0003, + 0x80100a0, + 0x16, + 0x2c, + 0x33, + 0x20043, + 0x2000200, + 0x4, + 0x60c, + 0xa1400, + 0x280000, + 0x6, + 0x46, + 0x70, + 0x610, + 0x12b, + 0x4001035, + 0x1010404, + 0x1e01, + 0x1e001e, + 0x1000100, + 0x100, + 0x0, + 0x5060403, + 0x1011108, + 0x1010101, + 0xf0a0a, + 0x0, + 0x0, + 0x4000000, + 0x4021008, + 0x4020206, + 0xc0034, + 0x100038, + 0x17003f, + 0x10001, + 0x10001, + 0x10005, + 0x20064, + 0x100010b, + 0x60006, + 0x650100, + 0x1000065, + 0x10c010c, + 0x1e1a1e1a, + 0x1011e1a, + 0xa070601, + 0xa07060d, + 0x100b080d, + 0xc00f, + 0xc01000, + 0xc01000, + 0x21000, + 0x120005, + 0x190064, + 0x10b, + 0x1100, + 0x1e1a0056, + 0x6000101, + 0x130204, + 0x1e1a0058, + 0x1000101, + 0x230408, + 0x1e1a005e, + 0x9000101, + 0x610, + 0x4040800, + 0x40100, + 0x3000277, + 0xa032001, + 0xa0a, + 0x80908, + 0x901, + 0x1100315c, + 0xa062002, + 0xa0a, + 0x141708, + 0x150d, + 0x2d00838e, + 0xf102004, + 0xf0b, + 0x8c, + 0x578, + 0xc20, + 0x7940, + 0x206a, + 0x14424, + 0x730006, + 0x3030133, + 0x4, + 0x0, + 0x4, + 0x1, + 0x5, + 0x2, + 0x6, + 0x50, + 0x1, + 0x5, + 0x28, + 0x73, + 0xd6, + 0x1, + 0x5, + 0x6b, + 0x1000133, + 0x140040, + 0x10001, + 0x1900040, + 0x1000c, + 0x42b0040, + 0x320, + 0x360014, + 0x1010101, + 0x2020101, + 0x8080404, + 0x67676767, + 0x67676767, + 0x67676767, + 0x67676767, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x5500, + 0x5a00, + 0x55003c, + 0x0, + 0x3c00005a, + 0x5500, + 0x5a00, + 0x55003c, + 0x0, + 0x3c00005a, + 0x18171615, + 0x14131211, + 0x7060504, + 0x3020100, + 0x0, + 0x0, + 0x0, + 0x1000000, + 0x4020201, + 0x80804, + 0x0, + 0x4, + 0x0, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x14, + 0x9, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x34, + 0x1b, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x4, + 0x0, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x14, + 0x9, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x34, + 0x1b, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x4, + 0x0, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x14, + 0x9, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x34, + 0x1b, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x4, + 0x0, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x14, + 0x9, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x34, + 0x1b, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, +}; + +void ddr_phy_train(u32 *phyreg) +{ + u32 i, len; + + len = sizeof(ddr_train_data) / sizeof(u32); + for (i = 0; i < len; i++) + out_le32(phyreg + i, ddr_train_data[i]); +} + diff --git a/drivers/ram/starfive/ddrphy_utils.c b/drivers/ram/starfive/ddrphy_utils.c new file mode 100644 index 0000000000..ed7667b536 --- /dev/null +++ b/drivers/ram/starfive/ddrphy_utils.c @@ -0,0 +1,1957 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong <yanhong.wang@starfivetech.com> + * + */ + +#include <common.h> +#include <asm/io.h> + +static u32 ddr_phy_data[] = { + 0x4f0, + 0x0, + 0x1030200, + 0x0, + 0x0, + 0x3000000, + 0x1000001, + 0x3000400, + 0x1000001, + 0x0, + 0x0, + 0x1000001, + 0x0, + 0xc00004, + 0xcc0008, + 0x660601, + 0x3, + 0x0, + 0x1, + 0xaaaa, + 0x5555, + 0xb5b5, + 0x4a4a, + 0x5656, + 0xa9a9, + 0xa9a9, + 0xb5b5, + 0x0, + 0x0, + 0x8000000, + 0x4000008, + 0x408, + 0xe4e400, + 0x71020, + 0xc0020, + 0x620, + 0x100, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x5555, + 0x1000100, + 0x800180, + 0x1, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x4, + 0x20, + 0x0, + 0x0, + 0x0, + 0x0, + 0x7ff0000, + 0x20008008, + 0x810, + 0x40100, + 0x0, + 0x1880c01, + 0x2003880c, + 0x20000125, + 0x7ff0200, + 0x101, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x20000, + 0x51515052, + 0x31c06000, + 0x11f0004, + 0xc0c001, + 0x3000000, + 0x30202, + 0x42100010, + 0x10c053e, + 0xf0c20, + 0x1000140, + 0xa30120, + 0xc00, + 0x210, + 0x200, + 0x2800000, + 0x80800101, + 0x3, + 0x76543210, + 0x8, + 0x2800280, + 0x2800280, + 0x2800280, + 0x2800280, + 0x280, + 0x8000, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x6e0080, + 0x1a00003, + 0x0, + 0x30000, + 0x80200, + 0x0, + 0x20202020, + 0x20202020, + 0x2020, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x4f0, + 0x0, + 0x1030200, + 0x0, + 0x0, + 0x3000000, + 0x1000001, + 0x3000400, + 0x1000001, + 0x0, + 0x0, + 0x1000001, + 0x0, + 0xc00004, + 0xcc0008, + 0x660601, + 0x3, + 0x0, + 0x1, + 0xaaaa, + 0x5555, + 0xb5b5, + 0x4a4a, + 0x5656, + 0xa9a9, + 0xa9a9, + 0xb5b5, + 0x0, + 0x0, + 0x8000000, + 0x4000008, + 0x408, + 0xe4e400, + 0x71020, + 0xc0020, + 0x620, + 0x100, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x5555, + 0x1000100, + 0x800180, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x4, + 0x20, + 0x0, + 0x0, + 0x0, + 0x0, + 0x7ff0000, + 0x20008008, + 0x810, + 0x40100, + 0x0, + 0x1880c01, + 0x2003880c, + 0x20000125, + 0x7ff0200, + 0x101, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x20000, + 0x51515052, + 0x31c06000, + 0x11f0004, + 0xc0c001, + 0x3000000, + 0x30202, + 0x42100010, + 0x10c053e, + 0xf0c20, + 0x1000140, + 0xa30120, + 0xc00, + 0x210, + 0x200, + 0x2800000, + 0x80800101, + 0x3, + 0x76543210, + 0x8, + 0x2800280, + 0x2800280, + 0x2800280, + 0x2800280, + 0x280, + 0x8000, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x6e0080, + 0x1a00003, + 0x0, + 0x30000, + 0x80200, + 0x0, + 0x20202020, + 0x20202020, + 0x2020, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 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0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x100, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x50000, + 0x4000000, + 0x55, + 0x0, + 0x0, + 0x0, + 0xf0001, + 0x280040, + 0x5002, + 0x10101, + 0x8008, + 0x81020, + 0x0, + 0x0, + 0x1000000, + 0x1, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x64, + 0x0, + 0x0, + 0x1010000, + 0x2020101, + 0x4040202, + 0x8080404, + 0xf0f0808, + 0xf0f0f0f, + 0x20200f0f, + 0x1b428000, + 0x4, + 0x1010000, + 0x1070501, + 0x54, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x64, + 0x0, + 0x108, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x3000000, + 0x0, + 0x0, + 0x0, + 0x4102035, + 0x41020, + 0x1c98c98, + 0x3f400000, + 0x3f3f1f3f, + 0x1f3f3f1f, + 0x1f3f3f, + 0x0, + 0x0, + 0x1, + 0x0, + 0x0, + 0x0, + 0x0, + 0x76543210, + 0x6010198, + 0x0, + 0x0, + 0x0, + 0x40700, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x2, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x1142, + 0x3020100, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x300, + 0x300, + 0x300, + 0x300, + 0x2, + 0x4011, + 0x4011, + 0x40, + 0x40, + 0x4011, + 0x1fff00, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x1004011, + 0x200400, + +}; + +void ddr_phy_util(u32 *phyreg) +{ + u32 i, len; + + len = sizeof(ddr_phy_data) / sizeof(u32); + for (i = 1792; i < len; i++) + out_le32(phyreg + i, ddr_phy_data[i]); + + for (i = 0; i < 1792; i++) + out_le32(phyreg + i, ddr_phy_data[i]); +} + diff --git a/drivers/ram/starfive/starfive_ddr.c b/drivers/ram/starfive/starfive_ddr.c new file mode 100644 index 0000000000..6cea01f063 --- /dev/null +++ b/drivers/ram/starfive/starfive_ddr.c @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong <yanhong.wang@starfivetech.com> + * + */ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <init.h> +#include <ram.h> +#include <syscon.h> +#include <asm/io.h> +#include <clk.h> +#include <wait_bit.h> +#include <linux/bitops.h> + +#include "starfive_ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct starfive_ddr_priv { + struct udevice *dev; + struct ram_info info; + void __iomem *ctrlreg; + void __iomem *phyreg; + u32 fre; +}; + +static void ddr_assert_rst(ulong addr, ulong addr_status, + u32 mask) +{ + uint32_t tmp; + + out_le32(addr, in_le32(addr) | mask); + do { + tmp = in_le32(addr_status); + } while ((tmp & mask) != 0); +} + +static void ddr_clear_rst(ulong addr, ulong addr_status, + u32 mask) +{ + uint32_t tmp; + + out_le32(addr, in_le32(addr) & (~mask)); + do { + tmp = in_le32(addr_status); + } while ((tmp & mask) != mask); +} + +static int starfive_ddr_setup(struct udevice *dev, struct starfive_ddr_priv *priv) +{ + ddr_phy_train(priv->phyreg + (2048 << 2)); + ddr_phy_util(priv->phyreg + (4096 << 2)); + ddr_phy_start(priv->phyreg); + + clrsetbits_le32(CLK_DDR_BUS_REG, CLK_DDR_BUS_MASK, 0<<24); + + ddrcsr_boot(priv->ctrlreg, priv->ctrlreg + 0x1000, priv->phyreg); + + return 0; +} + +static int starfive_ddr_probe(struct udevice *dev) +{ + struct starfive_ddr_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + int ret; + + priv->dev = dev; + addr = dev_read_addr_index(dev, 0); + priv->ctrlreg = (void __iomem *)addr; + addr = dev_read_addr_index(dev, 1); + priv->phyreg = (void __iomem *)addr; + ret = dev_read_u32(dev, "clock-frequency", &priv->fre); + if (ret) { + pr_err("clock-frequency not found in dt %d\n", ret); + return ret; + } + /* Read memory base and size from DT */ + fdtdec_setup_mem_size_base(); + priv->info.base = gd->ram_base; + priv->info.size = gd->ram_size; + + switch (priv->fre) { + case 2133: + clrsetbits_le32(CLK_DDR_BUS_REG, CLK_DDR_BUS_MASK, 0<<24); + clrsetbits_le32(SYS_SYSCON_40_REG, PLL1_PD_MASK, 1<<27); + clrsetbits_le32(SYS_SYSCON_36_REG, PLL1_DACPD_MASK, 0<<15); + clrsetbits_le32(SYS_SYSCON_36_REG, PLL1_DSMPD_MASK, 0<<16); + clrsetbits_le32(SYS_SYSCON_40_REG, PLL1_FRAC_MASK, 0xe00000<<0); + clrsetbits_le32(SYS_SYSCON_36_REG, PLL1_FBDIV_MASK, 0x58<<17); + clrsetbits_le32(SYS_SYSCON_44_REG, PLL1_PREDIV_MASK, 0x1<<0); + clrsetbits_le32(SYS_SYSCON_40_REG, PLL1_POSTDIV1_MASK, 0x1<<28); + clrsetbits_le32(SYS_SYSCON_40_REG, PLL1_PD_MASK, 0<<27); + udelay(100); + clrsetbits_le32(CLK_DDR_BUS_REG, CLK_DDR_BUS_MASK, (1<<24)&CLK_DDR_BUS_MASK); + + ddr_assert_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG, + RSTN_OSC_MASK); + ddr_clear_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG, + RSTN_OSC_MASK); + ddr_assert_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG, + RSTN_APB_MASK); + ddr_clear_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG, + RSTN_APB_MASK); + clrsetbits_le32(CLK_AXI_CTRL_REG, CLK_AXI_EN_MASK, (0<<31)&CLK_AXI_EN_MASK); + + ddr_assert_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG, + RSTN_AXI_MASK); + ddr_clear_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG, + RSTN_AXI_MASK); + + clrsetbits_le32(CLK_AXI_CTRL_REG, CLK_AXI_EN_MASK, (1<<31)&CLK_AXI_EN_MASK); + break; + + case 2800: + clrsetbits_le32(CLK_DDR_BUS_REG, CLK_DDR_BUS_MASK, 0<<24); + clrsetbits_le32(SYS_SYSCON_40_REG, PLL1_PD_MASK, 1<<27); + clrsetbits_le32(SYS_SYSCON_36_REG, PLL1_DACPD_MASK, 0<<15); + clrsetbits_le32(SYS_SYSCON_36_REG, PLL1_DSMPD_MASK, 0<<16); + clrsetbits_le32(SYS_SYSCON_40_REG, PLL1_FRAC_MASK, 0xAAAAAA<<0); + clrsetbits_le32(SYS_SYSCON_36_REG, PLL1_FBDIV_MASK, 0x74<<16); + clrsetbits_le32(SYS_SYSCON_44_REG, PLL1_PREDIV_MASK, 2<<0); + clrsetbits_le32(SYS_SYSCON_40_REG, PLL1_POSTDIV1_MASK, 0<<28); + clrsetbits_le32(SYS_SYSCON_40_REG, PLL1_PD_MASK, 0<<27); + + clrsetbits_le32(CLK_DDR_BUS_REG, CLK_DDR_BUS_MASK, 1<<24); + + ddr_assert_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG, + RSTN_OSC_MASK); + ddr_clear_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG, + RSTN_OSC_MASK); + ddr_assert_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG, + RSTN_APB_MASK); + ddr_clear_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG, + RSTN_APB_MASK); + ddr_assert_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG, + RSTN_AXI_MASK); + ddr_clear_rst(RESET_ASSERT1_REG, RESET_STATUS1_REG, + RSTN_AXI_MASK); + break; + default: + printk("Unknown DDR frequency %d\n", priv->fre); + break; + }; + + ret = starfive_ddr_setup(dev, priv); + printk("DDR version: f859e621d4eedc.\n"); + + return ret; +} + +static int starfive_ddr_get_info(struct udevice *dev, struct ram_info *info) +{ + struct starfive_ddr_priv *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops starfive_ddr_ops = { + .get_info = starfive_ddr_get_info, +}; + +static const struct udevice_id starfive_ddr_ids[] = { + { .compatible = "starfive,jh7110-ddr" }, + { } +}; + +U_BOOT_DRIVER(starfive_ddr) = { + .name = "starfive_ddr", + .id = UCLASS_RAM, + .of_match = starfive_ddr_ids, + .ops = &starfive_ddr_ops, + .probe = starfive_ddr_probe, + .priv_auto = sizeof(struct starfive_ddr_priv), +}; diff --git a/drivers/ram/starfive/starfive_ddr.h b/drivers/ram/starfive/starfive_ddr.h new file mode 100644 index 0000000000..01e89c148d --- /dev/null +++ b/drivers/ram/starfive/starfive_ddr.h @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong <yanhong.wang@starfivetech.com> + * + */ + +#ifndef __STARFIVE_DDR_H__ +#define __STARFIVE_DDR_H__ + +#include <common.h> +#include <asm/io.h> +#include <inttypes.h> + +#define SYS_CRG_BASE 0x13020000 +#define SYS_SYSCON_BASE 0x13030000 + +#define CLK_DDR_BUS_REG (SYS_CRG_BASE + 0xAC) +#define CLK_AXI_CTRL_REG (SYS_CRG_BASE + 0xB0) + +#define SYS_SYSCON_40_REG (SYS_SYSCON_BASE + 0x28) +#define SYS_SYSCON_36_REG (SYS_SYSCON_BASE + 0x24) +#define SYS_SYSCON_44_REG (SYS_SYSCON_BASE + 0x2c) + +#define RESET_ASSERT0_REG (SYS_CRG_BASE + 0x2F8) +#define RESET_ASSERT1_REG (SYS_CRG_BASE + 0x2FC) +#define RESET_ASSERT2_REG (SYS_CRG_BASE + 0x300) +#define RESET_ASSERT3_REG (SYS_CRG_BASE + 0x304) + +#define RESET_STATUS0_REG (SYS_CRG_BASE + 0x308) +#define RESET_STATUS1_REG (SYS_CRG_BASE + 0x30C) +#define RESET_STATUS2_REG (SYS_CRG_BASE + 0x310) +#define RESET_STATUS3_REG (SYS_CRG_BASE + 0x314) + +#define RSTN_AXI_MASK (0x1 << 6) +#define RSTN_OSC_MASK (0x1 << 7) +#define RSTN_APB_MASK (0x1 << 8) + +#define CLK_DDR_BUS_MASK 0x3000000U +#define PLL1_PD_MASK 0x8000000U +#define PLL1_DACPD_MASK 0x8000U +#define PLL1_DSMPD_MASK 0x10000U +#define PLL1_FRAC_MASK 0xFFFFFFU +#define PLL1_FBDIV_MASK 0x1FFE0000U +#define PLL1_PREDIV_MASK 0x3FU +#define PLL1_POSTDIV1_MASK 0x30000000U +#define CLK_AXI_EN_MASK 0x80000000U + +struct ddr_reg_set{ + u32 offset; + u32 val; +}; + +struct ddr_reg_clrset{ + u32 offset; + u32 mask; + u32 val; +}; + +void ddr_phy_train(u32 *phyreg); +void ddr_phy_util(u32 *phyreg); +void ddr_phy_start(u32 *phyreg); +void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg); + +#define DDR_REG_TRIGGER(addr, mask, value) \ + out_le32((addr), (in_le32(addr) & (mask)) | (value)) + +#endif /*__STARFIVE_DDR_H__*/ + |