diff options
| author | Dylan Hung <dylan_hung@aspeedtech.com> | 2023-02-21 16:01:09 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-03-07 01:03:56 +0300 |
| commit | 45443f6089e1e194bdd8f2aa351c72e32eb1d815 (patch) | |
| tree | ee224965f2031c69fb55f63a0a595c73f98e2b81 /drivers/ram | |
| parent | 94d30f476fe1eaf7b56595a4db961ba8e4200609 (diff) | |
| download | u-boot-45443f6089e1e194bdd8f2aa351c72e32eb1d815.tar.xz | |
ram: ast2600: Keep MPLL power on
According to the PLL vendor, we should keep the PLL power on, so we
shouldn't toggle the power-down bit during PLL initialization.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'drivers/ram')
| -rw-r--r-- | drivers/ram/aspeed/sdram_ast2600.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c index 1876755412..d463933363 100644 --- a/drivers/ram/aspeed/sdram_ast2600.c +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -1089,13 +1089,13 @@ static int ast2600_sdrammc_probe(struct udevice *dev) } reg = readl(&priv->scu->mpll); - reg &= ~(SCU_PLL_BYPASS | SCU_PLL_DIV_MASK | + reg &= ~(SCU_PLL_BYPASS | SCU_PLL_OFF | SCU_PLL_DIV_MASK | SCU_PLL_DENUM_MASK | SCU_PLL_NUM_MASK); - reg |= (SCU_PLL_RST | SCU_PLL_OFF | SCU_MPLL_FREQ_CFG); + reg |= (SCU_PLL_RST | SCU_MPLL_FREQ_CFG); writel(reg, &priv->scu->mpll); writel(SCU_MPLL_EXT_CFG, &priv->scu->mpll_ext); udelay(100); - reg &= ~(SCU_PLL_RST | SCU_PLL_OFF); + reg &= ~SCU_PLL_RST; writel(reg, &priv->scu->mpll); while ((readl(&priv->scu->mpll_ext) & BIT(31)) == 0) |