diff options
| author | Patrick Delaunay <patrick.delaunay@st.com> | 2020-03-06 13:14:10 +0300 |
|---|---|---|
| committer | Patrick Delaunay <patrick.delaunay@st.com> | 2020-03-24 16:23:26 +0300 |
| commit | d424e6786f637d3181ffa9e2cc9ed6bca00aa30f (patch) | |
| tree | 79614d29e4ff8ee049ac51ffd842ab86be38f328 /drivers/ram | |
| parent | b604a41c6bcfb6273e7478089ff3e7b65e233645 (diff) | |
| download | u-boot-d424e6786f637d3181ffa9e2cc9ed6bca00aa30f.tar.xz | |
ram: stm32mp1: reduce delay after BIST reset for tuning
Reduce the delay after BIST delay, from 1ms to 10us
which is enough accoriding datasheet.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'drivers/ram')
| -rw-r--r-- | drivers/ram/stm32mp1/stm32mp1_tuning.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ram/stm32mp1/stm32mp1_tuning.c b/drivers/ram/stm32mp1/stm32mp1_tuning.c index 07d57d496c..3013b7b667 100644 --- a/drivers/ram/stm32mp1/stm32mp1_tuning.c +++ b/drivers/ram/stm32mp1/stm32mp1_tuning.c @@ -402,7 +402,7 @@ run: writel(rand(), &phy->bistlsr); /* some delay to reset BIST */ - mdelay(1); + udelay(10); /*Perform BIST Run*/ clrsetbits_le32(&phy->bistrr, |