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author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2018-01-22 03:43:25 +0300 |
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committer | Marek Vasut <marex@denx.de> | 2018-01-25 01:27:21 +0300 |
commit | a6e25b2e12f954c40c76f5d024557ef409a9c4d5 (patch) | |
tree | 7d3b28043401c2526ab57e27636ad939de2cd972 /drivers/serial/serial_sh.h | |
parent | c493756ab4910b55af9dfe6682edce3af63ebf5c (diff) | |
download | u-boot-a6e25b2e12f954c40c76f5d024557ef409a9c4d5.tar.xz |
serial: sh: Unify CONFIG_R8A779[01234] as CONFIG_RCAR_GEN2
Use the common RCAR_GEN2 config option instead of enumerating
each SoC and having a lengthy ifdef clause. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers/serial/serial_sh.h')
-rw-r--r-- | drivers/serial/serial_sh.h | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 1b8d742f1c..229e331d72 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -224,9 +224,7 @@ struct uart_port { # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* Overrun error bit */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ - defined(CONFIG_R8A7792) || defined(CONFIG_R8A7793) || \ - defined(CONFIG_R8A7794) || defined(CONFIG_RCAR_GEN3) +#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) # if defined(CONFIG_SCIF_A) # define SCIF_ORER 0x0200 # else @@ -308,8 +306,7 @@ struct uart_port { /* SH7763 SCIF2 support */ # define SCIF2_RFDC_MASK 0x001f # define SCIF2_TXROOM_MAX 16 -#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \ - defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) +#elif defined(CONFIG_RCAR_GEN2) # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) # if defined(CONFIG_SCIF_A) # define SCIF_RFDC_MASK 0x007f @@ -566,8 +563,7 @@ SCIF_FNS(SCFCR, 0x18, 16) SCIF_FNS(SCFDR, 0x1c, 16) SCIF_FNS(SCLSR, 0x24, 16) SCIF_FNS(DL, 0x00, 0) /* dummy */ -#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \ - defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) +#elif defined(CONFIG_RCAR_GEN2) /* SCIFA and SCIF register offsets and size */ SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0) SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0) @@ -762,8 +758,7 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk) #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) #elif defined(__H8300H__) || defined(__H8300S__) #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) -#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \ - defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) +#elif defined(CONFIG_RCAR_GEN2) #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ #if defined(CONFIG_SCIF_A) #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */ |