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author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2019-05-01 19:20:00 +0300 |
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committer | Marek Vasut <marex@denx.de> | 2019-05-07 06:41:32 +0300 |
commit | 67180fe10102815924375d34bf6c6799e5ede8eb (patch) | |
tree | ef46cdb71c278ebe58ad77989fb7c7e1116b6b19 /drivers/serial | |
parent | 4d0732bf3c7b1d66084207a482897fa14619622b (diff) | |
download | u-boot-67180fe10102815924375d34bf6c6799e5ede8eb.tar.xz |
serial: sh: Add RZ/A1 support
Add support for RZ/A1 SoC specifics.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers/serial')
-rw-r--r-- | drivers/serial/serial_sh.c | 3 | ||||
-rw-r--r-- | drivers/serial/serial_sh.h | 3 |
2 files changed, 5 insertions, 1 deletions
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index e6fe5c7c67..8f52f9dce4 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -62,6 +62,9 @@ static void sh_serial_init_generic(struct uart_port *port) sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST); sci_in(port, SCFCR); sci_out(port, SCFCR, 0); +#if defined(CONFIG_RZA1) + sci_out(port, SCSPTR, 0x0003); +#endif } static void diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 887dd19ff5..8aa80d4a37 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -195,7 +195,7 @@ struct uart_port { # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ # endif # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -#elif defined(CONFIG_CPU_SH7269) +#elif defined(CONFIG_CPU_SH7269) || defined(CONFIG_RZA1) # define SCSPTR0 0xe8007020 /* 16 bit SCIF */ # define SCSPTR1 0xe8007820 /* 16 bit SCIF */ # define SCSPTR2 0xe8008020 /* 16 bit SCIF */ @@ -205,6 +205,7 @@ struct uart_port { # define SCSPTR6 0xe800a020 /* 16 bit SCIF */ # define SCSPTR7 0xe800a820 /* 16 bit SCIF */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +# define SCIF_ORER 0x0001 /* overrun error bit */ #elif defined(CONFIG_CPU_SH7619) # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ |