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| author | Fabio Estevam <fabio.estevam@nxp.com> | 2016-07-18 16:19:28 +0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-07-20 19:26:37 +0300 |
| commit | 8f2e2f15ffa1bb03b6e6e189312426059f3215d1 (patch) | |
| tree | 590d7251e471c82dbe64ba604c57bc5fea0803d4 /drivers/serial | |
| parent | 95cee94bd80c8dfbd5ac3b019782b55f4edebdeb (diff) | |
| download | u-boot-8f2e2f15ffa1bb03b6e6e189312426059f3215d1.tar.xz | |
mx6: clock: Fix the logic for reading axi_alt_sel
According to the IMX6DQRM Reference Manual, the description
of bit 7 (axi_alt_sel) of the CCM_CBCDR register is:
"AXI alternative clock select
0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock
1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock "
The current logic is inverted, so fix it to match the reference manual.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Diffstat (limited to 'drivers/serial')
0 files changed, 0 insertions, 0 deletions