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| author | Vignesh Raghavendra <vigneshr@ti.com> | 2021-06-07 17:17:51 +0300 |
|---|---|---|
| committer | Lokesh Vutla <lokeshvutla@ti.com> | 2021-06-11 16:48:52 +0300 |
| commit | 2af181b53e286e90c3b36ba608c1c7b209e8ad8e (patch) | |
| tree | 91ccb2d6b8f2a2e3e3ea6e615c06f30cdb64934d /drivers/soc | |
| parent | 00d6fc9c71e53ea2627e022ea55e02c0c676ad9c (diff) | |
| download | u-boot-2af181b53e286e90c3b36ba608c1c7b209e8ad8e.tar.xz | |
ARM: dts: k3: Add cfg register space for ringacc and udmap
R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING
CFG, TCHAN CFG and RCHAN CFG address ranges.
Note that these registers are present within respective IPs but are
not populated in Linux DT nodes (as they are configured via TISCI APIs)
and hence are added to -u-boot.dtsi for now.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-6-vigneshr@ti.com
Diffstat (limited to 'drivers/soc')
0 files changed, 0 insertions, 0 deletions