diff options
| author | Pratyush Yadav <p.yadav@ti.com> | 2021-06-25 22:17:08 +0300 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2021-06-28 09:27:10 +0300 |
| commit | a6903aa7ea98872ff66424051f85cdf0178c86f8 (patch) | |
| tree | 6ddeb563263d9cac5d04581d477b8e4e9be7c5da /drivers/spi/cadence_qspi.c | |
| parent | bd8c8dcd4d6fb1cf726d5a267be5ec33c93f1471 (diff) | |
| download | u-boot-a6903aa7ea98872ff66424051f85cdf0178c86f8.tar.xz | |
spi: cadence-qspi: Add a small delay before indirect writes
Once the start bit is toggled it takes a small amount of time before it
is internally synchronized. This means we can't start writing during
that part. So add a small delay to allow the bit to be synchronized.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers/spi/cadence_qspi.c')
| -rw-r--r-- | drivers/spi/cadence_qspi.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index de7628de27..a961193cdc 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -20,6 +20,8 @@ #include <linux/sizes.h> #include "cadence_qspi.h" +#define NSEC_PER_SEC 1000000000L + #define CQSPI_STIG_READ 0 #define CQSPI_STIG_WRITE 1 #define CQSPI_READ 2 @@ -208,6 +210,8 @@ static int cadence_spi_probe(struct udevice *bus) priv->qspi_is_init = 1; } + plat->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, plat->ref_clk_hz); + return 0; } |