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author | Pratyush Yadav <p.yadav@ti.com> | 2021-06-25 22:17:08 +0300 |
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committer | Jagan Teki <jagan@amarulasolutions.com> | 2021-06-28 09:27:10 +0300 |
commit | a6903aa7ea98872ff66424051f85cdf0178c86f8 (patch) | |
tree | 6ddeb563263d9cac5d04581d477b8e4e9be7c5da /drivers/spi/cadence_qspi_apb.c | |
parent | bd8c8dcd4d6fb1cf726d5a267be5ec33c93f1471 (diff) | |
download | u-boot-a6903aa7ea98872ff66424051f85cdf0178c86f8.tar.xz |
spi: cadence-qspi: Add a small delay before indirect writes
Once the start bit is toggled it takes a small amount of time before it
is internally synchronized. This means we can't start writing during
that part. So add a small delay to allow the bit to be synchronized.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers/spi/cadence_qspi_apb.c')
-rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index b051f462ed..92e57730bd 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -730,6 +730,12 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat, writel(CQSPI_REG_INDIRECTWR_START, plat->regbase + CQSPI_REG_INDIRECTWR); + /* + * Some delay is required for the above bit to be internally + * synchronized by the QSPI module. + */ + ndelay(plat->wr_delay); + while (remaining > 0) { write_bytes = remaining > page_size ? page_size : remaining; writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2); |