diff options
| author | Sean Anderson <seanga2@gmail.com> | 2020-10-17 01:57:47 +0300 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2020-12-18 13:46:37 +0300 |
| commit | 3004034989ac6d4752c384a5c74a69f37b8ce9d1 (patch) | |
| tree | 7bfb9965e3149c3f484017539d62956e9ddf97ca /drivers/spi/designware_spi.c | |
| parent | c785f43ffdf402ecd109bbce972c25e32bc4c85b (diff) | |
| download | u-boot-3004034989ac6d4752c384a5c74a69f37b8ce9d1.tar.xz | |
spi: dw: Rename registers to match datasheet
A few registers had slightly different names from what is in the datasheet.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers/spi/designware_spi.c')
| -rw-r--r-- | drivers/spi/designware_spi.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index e8ba80ef41..8abcdde8a3 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -27,14 +27,14 @@ #include <asm/io.h> /* Register offsets */ -#define DW_SPI_CTRL0 0x00 -#define DW_SPI_CTRL1 0x04 +#define DW_SPI_CTRLR0 0x00 +#define DW_SPI_CTRLR1 0x04 #define DW_SPI_SSIENR 0x08 #define DW_SPI_MWCR 0x0c #define DW_SPI_SER 0x10 #define DW_SPI_BAUDR 0x14 -#define DW_SPI_TXFLTR 0x18 -#define DW_SPI_RXFLTR 0x1c +#define DW_SPI_TXFTLR 0x18 +#define DW_SPI_RXFTLR 0x1c #define DW_SPI_TXFLR 0x20 #define DW_SPI_RXFLR 0x24 #define DW_SPI_SR 0x28 @@ -191,13 +191,13 @@ static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv) u32 fifo; for (fifo = 1; fifo < 256; fifo++) { - dw_write(priv, DW_SPI_TXFLTR, fifo); - if (fifo != dw_read(priv, DW_SPI_TXFLTR)) + dw_write(priv, DW_SPI_TXFTLR, fifo); + if (fifo != dw_read(priv, DW_SPI_TXFTLR)) break; } priv->fifo_len = (fifo == 1) ? 0 : fifo; - dw_write(priv, DW_SPI_TXFLTR, 0); + dw_write(priv, DW_SPI_TXFTLR, 0); } dev_dbg(bus, "fifo_len=%d\n", priv->fifo_len); } @@ -443,8 +443,8 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen, dev_dbg(dev, "cr0=%08x rx=%p tx=%p len=%d [bytes]\n", cr0, rx, tx, priv->len); /* Reprogram cr0 only if changed */ - if (dw_read(priv, DW_SPI_CTRL0) != cr0) - dw_write(priv, DW_SPI_CTRL0, cr0); + if (dw_read(priv, DW_SPI_CTRLR0) != cr0) + dw_write(priv, DW_SPI_CTRLR0, cr0); /* * Configure the desired SS (slave select 0...3) in the controller |