spi: ich: Support hardware sequencing

Apollo Lake (APL) only supports hardware sequencing. Add support for this
into the SPI driver, as an option.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

1 files changed, 39 insertions, 0 deletions

diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
index 623b2c547a..c7cf37b932 100644
--- a/drivers/spi/ich.h
+++ b/drivers/spi/ich.h
@@ -163,6 +163,45 @@ struct spi_trans {
 
 #define ICH_BOUNDARY	0x1000
 
+#define HSFSTS_FDBC_SHIFT	24
+#define HSFSTS_FDBC_MASK	(0x3f << HSFSTS_FDBC_SHIFT)
+#define HSFSTS_WET		BIT(21)
+#define HSFSTS_FCYCLE_SHIFT	17
+#define HSFSTS_FCYCLE_MASK	(0xf << HSFSTS_FCYCLE_SHIFT)
+
+/* Supported flash cycle types */
+enum hsfsts_cycle_t {
+	HSFSTS_CYCLE_READ	= 0,
+	HSFSTS_CYCLE_WRITE	= 2,
+	HSFSTS_CYCLE_4K_ERASE,
+	HSFSTS_CYCLE_64K_ERASE,
+	HSFSTS_CYCLE_RDSFDP,
+	HSFSTS_CYCLE_RDID,
+	HSFSTS_CYCLE_WR_STATUS,
+	HSFSTS_CYCLE_RD_STATUS,
+};
+
+#define HSFSTS_FGO		BIT(16)
+#define HSFSTS_FLOCKDN		BIT(15)
+#define HSFSTS_FDV		BIT(14)
+#define HSFSTS_FDOPSS		BIT(13)
+#define HSFSTS_WRSDIS		BIT(11)
+#define HSFSTS_SAF_CE		BIT(8)
+#define HSFSTS_SAF_ACTIVE	BIT(7)
+#define HSFSTS_SAF_LE		BIT(6)
+#define HSFSTS_SCIP		BIT(5)
+#define HSFSTS_SAF_DLE		BIT(4)
+#define HSFSTS_SAF_ERROR	BIT(3)
+#define HSFSTS_AEL		BIT(2)
+#define HSFSTS_FCERR		BIT(1)
+#define HSFSTS_FDONE		BIT(0)
+#define HSFSTS_W1C_BITS		0xff
+
+/* Maximum bytes of data that can fit in FDATAn (0x10) registers */
+#define SPIBAR_FDATA_FIFO_SIZE		0x40
+
+#define SPIBAR_HWSEQ_XFER_TIMEOUT_MS	5000
+
 enum ich_version {
 	ICHV_7,
 	ICHV_9,