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authorTom Rini <trini@konsulko.com>2023-04-29 16:29:41 +0300
committerTom Rini <trini@konsulko.com>2023-04-29 16:29:41 +0300
commitfe3a77cb157a6210d8036845f5f80ea67c183563 (patch)
tree1d53e64cbcdf10c6e5dfb95cefd098e643820bed /drivers/spi/mpc8xxx_spi.c
parent076f13308c6f06e2c4feb8b408e997bc732586e1 (diff)
parent4d0c8db74d83e43dec4e7481b2d1e194f51d907b (diff)
downloadu-boot-fe3a77cb157a6210d8036845f5f80ea67c183563.tar.xz
Merge branch 'for-2023.07' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx
This pull request adds support for the last CPU board from CS GROUP France (previously CSSI). That CPU board called CMPCPRO has a mpc8321E CPU (Family PQII PRO hence its name) and can be plugged in place of the CMPC885 board. In order to support that new board, the following changes are included in this series: - Make the mpc8xx watchdog driver more generic for reusing it with mpc83xx - Fix various small problems on mpc83xx platform - Add a GPIO Driver for QE GPIOs - Add support for mpc832x into mpc83xx SPI driver - Refactor existing board code that will be shared with new board - Add the new board
Diffstat (limited to 'drivers/spi/mpc8xxx_spi.c')
-rw-r--r--drivers/spi/mpc8xxx_spi.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c
index 6869d60d97..78892173dc 100644
--- a/drivers/spi/mpc8xxx_spi.c
+++ b/drivers/spi/mpc8xxx_spi.c
@@ -16,6 +16,7 @@
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <asm/arch/soc.h>
enum {
SPI_EV_NE = BIT(31 - 22), /* Receiver Not Empty */
@@ -30,6 +31,7 @@ enum {
SPI_MODE_REV = BIT(31 - 5), /* Reverse mode - MSB first */
SPI_MODE_MS = BIT(31 - 6), /* Always master */
SPI_MODE_EN = BIT(31 - 7), /* Enable interface */
+ SPI_MODE_OP = BIT(31 - 17), /* CPU Mode, QE otherwise */
SPI_MODE_LEN_MASK = 0xf00000,
SPI_MODE_LEN_SHIFT = 20,
@@ -89,6 +91,9 @@ static int mpc8xxx_spi_probe(struct udevice *dev)
*/
out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS);
+ if (dev_get_driver_data(dev) == SOC_MPC832X)
+ setbits_be32(&priv->spi->mode, SPI_MODE_OP);
+
/* set len to 8 bits */
setbits_be32(&spi->mode, (8 - 1) << SPI_MODE_LEN_SHIFT);
@@ -130,6 +135,7 @@ static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen,
u32 tmpdin = 0, tmpdout = 0, n;
const u8 *cout = dout;
u8 *cin = din;
+ ulong type = dev_get_driver_data(bus);
debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__,
bus->name, plat->cs, (uint)dout, (uint)din, bitlen);
@@ -157,6 +163,9 @@ static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen,
if (cout)
tmpdout = *cout++;
+ if (type == SOC_MPC832X)
+ tmpdout <<= 24;
+
/* Write the data out */
out_be32(&spi->tx, tmpdout);
@@ -179,6 +188,9 @@ static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen,
tmpdin = in_be32(&spi->rx);
setbits_be32(&spi->event, SPI_EV_NE);
+ if (type == SOC_MPC832X)
+ tmpdin >>= 16;
+
if (cin)
*cin++ = tmpdin;
@@ -271,6 +283,7 @@ static const struct dm_spi_ops mpc8xxx_spi_ops = {
static const struct udevice_id mpc8xxx_spi_ids[] = {
{ .compatible = "fsl,spi" },
+ { .compatible = "fsl,mpc832x-spi", .data = SOC_MPC832X },
{ }
};