diff options
author | Stephen Warren <swarren@nvidia.com> | 2016-06-17 18:44:00 +0300 |
---|---|---|
committer | Simon Glass <sjg@chromium.org> | 2016-06-20 02:05:55 +0300 |
commit | 135aa95002646c46e89de93fa36adad1b010548f (patch) | |
tree | b601e08f7d91c7e2cda127d59f8f81128d0cb1ac /drivers/spi/rk_spi.c | |
parent | 4581b717b1bf0fb04e7d9fcaf3d4c23d357154ac (diff) | |
download | u-boot-135aa95002646c46e89de93fa36adad1b010548f.tar.xz |
clk: convert API to match reset/mailbox style
The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock
provider now implements a single set of clocks. This provides a simpler
conceptual interface to clients, and better aligns with device tree
clock bindings.
* Clocks are now identified with a single "struct clk", rather than
requiring clients to store the clock provider device and clock identity
values separately. For simple clock consumers, this isolates clients
from internal details of the clock API.
* clk.h is split so it only contains the client/consumer API, whereas
clk-uclass.h contains the provider API. This aligns with the recently
added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers
can customize these operations if needed. This also aligns with the
recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and
clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.
Buildman shows no clock-related errors for any board for which buildman
can download a toolchain.
test/py passes for sandbox (which invokes the dm clk test amongst
others).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/spi/rk_spi.c')
-rw-r--r-- | drivers/spi/rk_spi.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index 9eff423acd..bc6dfd8862 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -35,8 +35,7 @@ struct rockchip_spi_platdata { struct rockchip_spi_priv { struct rockchip_spi *regs; - struct udevice *clk; - int clk_id; + struct clk clk; unsigned int max_freq; unsigned int mode; ulong last_transaction_us; /* Time of last transaction end */ @@ -144,7 +143,6 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) bus->name, ret); return ret; } - priv->clk_id = ret; plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 50000000); @@ -175,7 +173,7 @@ static int rockchip_spi_probe(struct udevice *bus) * Use 99 MHz as our clock since it divides nicely into 594 MHz which * is the assumed speed for CLK_GENERAL. */ - ret = clk_set_periph_rate(priv->clk, priv->clk_id, 99000000); + ret = clk_set_rate(&priv->clk, 99000000); if (ret < 0) { debug("%s: Failed to set clock: %d\n", __func__, ret); return ret; |