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author | Tom Rini <trini@konsulko.com> | 2021-11-16 17:51:04 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2021-11-16 17:51:04 +0300 |
commit | 2ffa0e87df3a7595f71d05782924ee83146d9fe7 (patch) | |
tree | 4c0b1046ff1ef79e658c77a6b9342d87d53beb61 /drivers/spi | |
parent | 9272805139a104c83dff8230e03e9626dd9bc195 (diff) | |
parent | 11c0255cd8a7177e2b714040efcfd51844cb5d8e (diff) | |
download | u-boot-2ffa0e87df3a7595f71d05782924ee83146d9fe7.tar.xz |
Merge tag 'xilinx-for-v2022.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.01-rc3
sdhci:
- Fix emmc mini case with missing firmware interface
zynqmp:
- Restore JTAG interface if required
- Allow overriding board name
- Add support for DLC21
- Fix one fallthrought statement description
- Use config macro instead of name duplication
- Save multiboot to variable
firmware:
- Handle ipi_req errors better
- Use local buffer in case user doesn't need it instead of NULL/0 location
spi:
- gqsi: Fix write issue at low frequencies
net:
- gem: Disable broadcasts
Diffstat (limited to 'drivers/spi')
-rw-r--r-- | drivers/spi/zynqmp_gqspi.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 2db4ae20f1..c772bae3cc 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -37,6 +37,7 @@ */ #define GQSPI_IXR_TXNFULL_MASK 0x00000004 /* QSPI TX FIFO Overflow */ #define GQSPI_IXR_TXFULL_MASK 0x00000008 /* QSPI TX FIFO is full */ +#define GQSPI_IXR_TXFIFOEMPTY_MASK 0x00000100 /* QSPI TX FIFO is Empty */ #define GQSPI_IXR_RXNEMTY_MASK 0x00000010 /* QSPI RX FIFO Not Empty */ #define GQSPI_IXR_GFEMTY_MASK 0x00000080 /* QSPI Generic FIFO Empty */ #define GQSPI_IXR_GFNFULL_MASK 0x00000200 /* QSPI GENFIFO not full */ @@ -279,9 +280,6 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on) debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg); - /* Dummy generic FIFO entry */ - zynqmp_qspi_fill_gen_fifo(priv, 0); - zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg); } @@ -470,6 +468,13 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size) } } + ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXFIFOEMPTY_MASK, 1, + GQSPI_TIMEOUT, 1); + if (ret) { + printf("%s: Timeout\n", __func__); + return ret; + } + priv->tx_buf += len; return 0; } |