Merge tag 'v2021.10-rc4' into next

Prepare v2021.10-rc4

Signed-off-by: Tom Rini <trini@konsulko.com>

# gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT
# gpg:                using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C
# gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate]

# Conflicts:
#	board/Arcturus/ucp1020/spl.c
#	cmd/mvebu/Kconfig
#	common/Kconfig.boot
#	common/image-fit.c
#	configs/UCP1020_defconfig
#	configs/sifive_unmatched_defconfig
#	drivers/pci/Kconfig
#	include/configs/UCP1020.h
#	include/configs/sifive-unmatched.h
#	lib/Makefile
#	scripts/config_whitelist.txt

2 files changed, 15 insertions, 17 deletions

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index e12699bec7..d07e9a28af 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -271,7 +271,7 @@ config NXP_FSPI
 
 config OCTEON_SPI
 	bool "Octeon SPI driver"
-	depends on DM_PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2)
+	depends on ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2
 	help
 	  Enable the Octeon SPI driver. This driver can be used to
 	  access the SPI NOR flash on Octeon II/III and OcteonTX/TX2
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index fc81b07343..2db4ae20f1 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -77,6 +77,7 @@
 
 #define GQSPI_GFIFO_SELECT		BIT(0)
 #define GQSPI_FIFO_THRESHOLD		1
+#define GQSPI_GENFIFO_THRESHOLD		31
 
 #define SPI_XFER_ON_BOTH		0
 #define SPI_XFER_ON_LOWER		1
@@ -197,14 +198,15 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
 	writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->idisr);
 	writel(GQSPI_FIFO_THRESHOLD, &regs->txftr);
 	writel(GQSPI_FIFO_THRESHOLD, &regs->rxftr);
+	writel(GQSPI_GENFIFO_THRESHOLD, &regs->gqfthr);
 	writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->isr);
+	writel(~GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 
 	config_reg = readl(&regs->confr);
 	config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
 			GQSPI_CONFIG_MODE_EN_MASK);
-	config_reg |= GQSPI_CONFIG_DMA_MODE |
-		      GQSPI_GFIFO_WP_HOLD |
-		      GQSPI_DFLT_BAUD_RATE_DIV;
+	config_reg |= GQSPI_CONFIG_DMA_MODE | GQSPI_GFIFO_WP_HOLD |
+		      GQSPI_DFLT_BAUD_RATE_DIV | GQSPI_GFIFO_STRT_MODE_MASK;
 	writel(config_reg, &regs->confr);
 
 	writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
@@ -242,6 +244,8 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
 	u32 config_reg, ier;
 	int ret = 0;
 
+	writel(gqspi_fifo_reg, &regs->genfifo);
+
 	config_reg = readl(&regs->confr);
 	/* Manual start if needed */
 	config_reg |= GQSPI_STRT_GEN_FIFO;
@@ -249,16 +253,15 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
 
 	/* Enable interrupts */
 	ier = readl(&regs->ier);
-	ier |= GQSPI_IXR_GFNFULL_MASK;
+	ier |= GQSPI_IXR_GFEMTY_MASK;
 	writel(ier, &regs->ier);
 
-	/* Wait until the fifo is not full to write the new command */
-	ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFNFULL_MASK, 1,
+	/* Wait until the gen fifo is empty to write the new command */
+	ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFEMTY_MASK, 1,
 				GQSPI_TIMEOUT, 1);
 	if (ret)
 		printf("%s Timeout\n", __func__);
 
-	writel(gqspi_fifo_reg, &regs->genfifo);
 }
 
 static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
@@ -572,25 +575,20 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
 				 u32 gen_fifo_cmd, u32 *buf)
 {
 	u32 addr;
-	u32 size, len;
+	u32 size;
 	u32 actuallen = priv->len;
 	int ret = 0;
 	struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
 
 	writel((unsigned long)buf, &dma_regs->dmadst);
-	writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize);
+	writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize);
 	writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
 	addr = (unsigned long)buf;
-	size = roundup(priv->len, ARCH_DMA_MINALIGN);
+	size = roundup(priv->len, GQSPI_DMA_ALIGN);
 	flush_dcache_range(addr, addr + size);
 
 	while (priv->len) {
-		len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
-		if (!(gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) &&
-		    (len % ARCH_DMA_MINALIGN)) {
-			gen_fifo_cmd &= ~GENMASK(7, 0);
-			gen_fifo_cmd |= roundup(len, ARCH_DMA_MINALIGN);
-		}
+		zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 		zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 
 		debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);