diff options
| author | Peng Fan <van.freenix@gmail.com> | 2016-01-04 16:12:22 +0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-01-07 19:53:11 +0300 |
| commit | fcbe8c56743a1f8ec397a71d5a932faee920bc8a (patch) | |
| tree | 3a210075022ec5bdd6762def2a1e4cc0af7de8c6 /drivers/thermal/imx_thermal.c | |
| parent | ce2190f52523f36e42b702a5b59eb202aae565b2 (diff) | |
| download | u-boot-fcbe8c56743a1f8ec397a71d5a932faee920bc8a.tar.xz | |
imx: mx7: fix the temperature checking for Rev1.1
To TO1.0, we can not rely on finish bit to read temperature. But to
TO1.1, the issue was fixed by IC, we can rely on finish bit for
temperature reading for TO1.1.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Adrian Alonso <aalonso@freescale.com>
Diffstat (limited to 'drivers/thermal/imx_thermal.c')
| -rw-r--r-- | drivers/thermal/imx_thermal.c | 23 |
1 files changed, 15 insertions, 8 deletions
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 09a3c52680..0509094555 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -130,7 +130,7 @@ static int read_cpu_temperature(struct udevice *dev) #elif defined(CONFIG_MX7) static int read_cpu_temperature(struct udevice *dev) { - unsigned int reg, tmp, start; + unsigned int reg, tmp; unsigned int raw_25c, te1; int temperature; unsigned int *priv = dev_get_priv(dev); @@ -169,18 +169,25 @@ static int read_cpu_temperature(struct udevice *dev) writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set); - start = get_timer(0); - /* Wait max 100ms */ - do { + if (soc_rev() >= CHIP_REV_1_1) { + while ((readl(&ccm_anatop->tempsense1) & + TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK) == 0) + ; + reg = readl(&ccm_anatop->tempsense1); + tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) + >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT; + } else { /* - * Since we can not rely on finish bit, use 1ms delay to get - * temperature. From RM, 17us is enough to get data, but - * to gurantee to get the data, delay 100ms here. + * Since we can not rely on finish bit, use 10ms + * delay to get temperature. From RM, 17us is + * enough to get data, but to gurantee to get + * the data, delay 10ms here. */ + udelay(10000); reg = readl(&ccm_anatop->tempsense1); tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT; - } while (get_timer(0) < (start + 100)); + } writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); |