diff options
| author | Giulio Benetti <giulio.benetti@benettiengineering.com> | 2020-04-08 18:10:16 +0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2020-04-18 13:54:43 +0300 |
| commit | e121e00352215834d45a2b5eec82a1feaac310df (patch) | |
| tree | fbb36cfb84fe29c92af2465625d0f512f1051400 /drivers/video/mxsfb.c | |
| parent | abda0a5a22f5a090a169649aeb300d6f4bdee770 (diff) | |
| download | u-boot-e121e00352215834d45a2b5eec82a1feaac310df.tar.xz | |
video: mxsfb: enable setting HSYNC negative polarity
HSYNC signal can now be flipped according to display_flags bitmaks by
writing its bitmask on vdctrl0 register.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Diffstat (limited to 'drivers/video/mxsfb.c')
| -rw-r--r-- | drivers/video/mxsfb.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index cdd6dfaced..9912cf3d82 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -57,8 +57,10 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr, struct display_timing *timings, int bpp) { struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + const enum display_flags flags = timings->flags; uint32_t word_len = 0, bus_width = 0; uint8_t valid_data = 0; + uint32_t vdctrl0; #if CONFIG_IS_ENABLED(CLK) struct clk per_clk; @@ -118,10 +120,14 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr, writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | timings->hactive.typ, ®s->hw_lcdif_transfer_count); - writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL | - LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | - LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | - timings->vsync_len.typ, ®s->hw_lcdif_vdctrl0); + vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL | + LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | + timings->vsync_len.typ; + + if(flags & DISPLAY_FLAGS_HSYNC_HIGH) + vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL; + writel(vdctrl0, ®s->hw_lcdif_vdctrl0); writel(timings->vback_porch.typ + timings->vfront_porch.typ + timings->vsync_len.typ + timings->vactive.typ, ®s->hw_lcdif_vdctrl1); |