diff options
author | Suneel Garapati <sgarapati@marvell.com> | 2019-10-22 02:09:36 +0300 |
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committer | Stefan Roese <sr@denx.de> | 2020-08-25 09:01:16 +0300 |
commit | af6ba90048afb4e0db3ff2480364286f230f8b91 (patch) | |
tree | 6cb97435316adc6349f6565a895a05b15fe525f2 /drivers/watchdog/octeontx_wdt.c | |
parent | 708598997db23d111b7693ed95454d990a82b3d5 (diff) | |
download | u-boot-af6ba90048afb4e0db3ff2480364286f230f8b91.tar.xz |
watchdog: Add reset support for OcteonTX / TX2
Adds support for Core 0 watchdog poke on OcteonTX and OcteonTX2
platforms.
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/watchdog/octeontx_wdt.c')
-rw-r--r-- | drivers/watchdog/octeontx_wdt.c | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/drivers/watchdog/octeontx_wdt.c b/drivers/watchdog/octeontx_wdt.c new file mode 100644 index 0000000000..1e0670e0c5 --- /dev/null +++ b/drivers/watchdog/octeontx_wdt.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include <dm.h> +#include <errno.h> +#include <wdt.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define CORE0_POKE_OFFSET 0x50000 +#define CORE0_POKE_OFFSET_MASK 0xfffffULL + +struct octeontx_wdt { + void __iomem *reg; +}; + +static int octeontx_wdt_reset(struct udevice *dev) +{ + struct octeontx_wdt *priv = dev_get_priv(dev); + + writeq(~0ULL, priv->reg); + + return 0; +} + +static int octeontx_wdt_probe(struct udevice *dev) +{ + struct octeontx_wdt *priv = dev_get_priv(dev); + + priv->reg = dev_remap_addr(dev); + if (!priv->reg) + return -EINVAL; + + /* + * Save core poke register address in reg (its not 0xa0000 as + * extracted from the DT but 0x50000 instead) + */ + priv->reg = (void __iomem *)(((u64)priv->reg & + ~CORE0_POKE_OFFSET_MASK) | + CORE0_POKE_OFFSET); + + return 0; +} + +static const struct wdt_ops octeontx_wdt_ops = { + .reset = octeontx_wdt_reset, +}; + +static const struct udevice_id octeontx_wdt_ids[] = { + { .compatible = "arm,sbsa-gwdt" }, + {} +}; + +U_BOOT_DRIVER(wdt_octeontx) = { + .name = "wdt_octeontx", + .id = UCLASS_WDT, + .of_match = octeontx_wdt_ids, + .ops = &octeontx_wdt_ops, + .priv_auto_alloc_size = sizeof(struct octeontx_wdt), + .probe = octeontx_wdt_probe, +}; |