diff options
author | Tom Rini <trini@konsulko.com> | 2021-07-17 17:52:21 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2021-07-17 17:52:21 +0300 |
commit | d5dbc661c3041e910e161a95fca9e615d85730ac (patch) | |
tree | aff587483c785b8384de496d6670e9824eb3e703 /drivers/watchdog | |
parent | c39946a2e2d062025c9fc8b34587dfdd45fd8703 (diff) | |
parent | edf95bdeddeab8f0fd7b88d4865fbc6e99071c73 (diff) | |
download | u-boot-d5dbc661c3041e910e161a95fca9e615d85730ac.tar.xz |
Merge tag 'u-boot-imx-20210717' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
i.MX
----
- mx7ulp : fix WDOG
- imx8 : Phytec
- USB3 support for i.MX8
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
Diffstat (limited to 'drivers/watchdog')
-rw-r--r-- | drivers/watchdog/ulp_wdog.c | 57 |
1 files changed, 37 insertions, 20 deletions
diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index 6f63b11b9f..ecd35ef22a 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -12,9 +12,7 @@ * MX7ULP WDOG Register Map */ struct wdog_regs { - u8 cs1; - u8 cs2; - u16 reserve0; + u32 cs; u32 cnt; u32 toval; u32 win; @@ -30,10 +28,12 @@ struct wdog_regs { #define UNLOCK_WORD0 0xC520 /* 1st unlock word */ #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */ -#define WDGCS1_WDGE (1<<7) -#define WDGCS1_WDGUPDATE (1<<5) +#define WDGCS_WDGE BIT(7) +#define WDGCS_WDGUPDATE BIT(5) -#define WDGCS2_FLG (1<<6) +#define WDGCS_RCS BIT(10) +#define WDGCS_ULK BIT(11) +#define WDGCS_FLG BIT(14) #define WDG_BUS_CLK (0x0) #define WDG_LPO_CLK (0x1) @@ -52,27 +52,34 @@ void hw_watchdog_reset(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - writel(REFRESH_WORD0, &wdog->cnt); - writel(REFRESH_WORD1, &wdog->cnt); + dmb(); + __raw_writel(REFRESH_WORD0, &wdog->cnt); + __raw_writel(REFRESH_WORD1, &wdog->cnt); + dmb(); } void hw_watchdog_init(void) { - u8 val; struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - writel(UNLOCK_WORD0, &wdog->cnt); - writel(UNLOCK_WORD1, &wdog->cnt); + dmb(); + __raw_writel(UNLOCK_WORD0, &wdog->cnt); + __raw_writel(UNLOCK_WORD1, &wdog->cnt); + dmb(); - val = readb(&wdog->cs2); - val |= WDGCS2_FLG; - writeb(val, &wdog->cs2); + /* Wait WDOG Unlock */ + while (!(readl(&wdog->cs) & WDGCS_ULK)) + ; hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS); writel(0, &wdog->win); - writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ - writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */ + /* setting 1-kHz clock source, enable counter running, and clear interrupt */ + writel((WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs); + + /* Wait WDOG reconfiguration */ + while (!(readl(&wdog->cs) & WDGCS_RCS)) + ; hw_watchdog_reset(); } @@ -81,14 +88,24 @@ void reset_cpu(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - writel(UNLOCK_WORD0, &wdog->cnt); - writel(UNLOCK_WORD1, &wdog->cnt); + dmb(); + __raw_writel(UNLOCK_WORD0, &wdog->cnt); + __raw_writel(UNLOCK_WORD1, &wdog->cnt); + dmb(); + + /* Wait WDOG Unlock */ + while (!(readl(&wdog->cs) & WDGCS_ULK)) + ; hw_watchdog_set_timeout(5); /* 5ms timeout */ writel(0, &wdog->win); - writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ - writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */ + /* enable counter running */ + writel((WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs); + + /* Wait WDOG reconfiguration */ + while (!(readl(&wdog->cs) & WDGCS_RCS)) + ; hw_watchdog_reset(); |