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author | Tom Rini <trini@konsulko.com> | 2021-02-23 18:45:55 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2021-02-23 18:45:55 +0300 |
commit | cbe607b920bc0827d8fe379ed4f5ae4e2058513e (patch) | |
tree | b8cdbb8856766675f37bb92f27ab9c662fa647f9 /drivers/watchdog | |
parent | 8f7a16aac36c2a38956bd04b53cb7b94b7a70180 (diff) | |
parent | d9aa19efa8a6c20d51b7884de0a7f8dae3f835d2 (diff) | |
download | u-boot-cbe607b920bc0827d8fe379ed4f5ae4e2058513e.tar.xz |
Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.04-rc3
qspi:
- Support for dual/quad mode
- Fix speed handling
clk:
- Add clock enable function for zynq/zynqmp/versal
gem:
- Enable clock for Versal
- Fix error path
- Fix mdio deregistration path
fpga:
- Fix buffer alignment for ZynqMP
xilinx:
- Fix reset reason clearing in ZynqMP
- Show silicon version in SPL for Zynq/ZynqMP
- Fix DTB selection for ZynqMP
- Rename zc1275 to zcu1275 to match DT name
Diffstat (limited to 'drivers/watchdog')
-rw-r--r-- | drivers/watchdog/xilinx_wwdt.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c index 9137d87697..11b30ae85d 100644 --- a/drivers/watchdog/xilinx_wwdt.c +++ b/drivers/watchdog/xilinx_wwdt.c @@ -90,9 +90,8 @@ static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags) /* Calculate timeout count */ count = timeout * clock_f; - /* clk_enable will return -ENOSYS when it is not implemented */ ret = clk_enable(&wdt->clk); - if (ret && ret != -ENOSYS) { + if (ret) { dev_err(dev, "failed to enable clock\n"); return ret; } |