Merge tag 'v2021.10-rc4' into next

Prepare v2021.10-rc4

Signed-off-by: Tom Rini <trini@konsulko.com>

# gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT
# gpg:                using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C
# gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate]

# Conflicts:
#	board/Arcturus/ucp1020/spl.c
#	cmd/mvebu/Kconfig
#	common/Kconfig.boot
#	common/image-fit.c
#	configs/UCP1020_defconfig
#	configs/sifive_unmatched_defconfig
#	drivers/pci/Kconfig
#	include/configs/UCP1020.h
#	include/configs/sifive-unmatched.h
#	lib/Makefile
#	scripts/config_whitelist.txt

25 files changed, 226 insertions, 235 deletions

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index d4047c04f5..2062197afc 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -170,13 +170,8 @@ int ahci_reset(void __iomem *base)
 static int ahci_host_init(struct ahci_uc_priv *uc_priv)
 {
 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
-# ifdef CONFIG_DM_PCI
 	struct udevice *dev = uc_priv->dev;
 	struct pci_child_plat *pplat = dev_get_parent_plat(dev);
-# else
-	pci_dev_t pdev = uc_priv->dev;
-	unsigned short vendor;
-# endif
 	u16 tmp16;
 #endif
 	void __iomem *mmio = uc_priv->mmio_base;
@@ -200,23 +195,12 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv)
 	writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
 
 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
-# ifdef CONFIG_DM_PCI
 	if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
 		u16 tmp16;
 
 		dm_pci_read_config16(dev, 0x92, &tmp16);
 		dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
 	}
-# else
-	pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
-
-	if (vendor == PCI_VENDOR_ID_INTEL) {
-		u16 tmp16;
-		pci_read_config_word(pdev, 0x92, &tmp16);
-		tmp16 |= 0xf;
-		pci_write_config_word(pdev, 0x92, tmp16);
-	}
-# endif
 #endif
 	uc_priv->cap = readl(mmio + HOST_CAP);
 	uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
@@ -331,15 +315,9 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv)
 	debug("HOST_CTL 0x%x\n", tmp);
 #if !defined(CONFIG_DM_SCSI)
 #ifndef CONFIG_SCSI_AHCI_PLAT
-# ifdef CONFIG_DM_PCI
 	dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
 	tmp |= PCI_COMMAND_MASTER;
 	dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
-# else
-	pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
-	tmp |= PCI_COMMAND_MASTER;
-	pci_write_config_word(pdev, PCI_COMMAND, tmp16);
-# endif
 #endif
 #endif
 	return 0;
@@ -349,11 +327,7 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv)
 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
 {
 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
-# if defined(CONFIG_DM_PCI)
 	struct udevice *dev = uc_priv->dev;
-# else
-	pci_dev_t pdev = uc_priv->dev;
-# endif
 	u16 cc;
 #endif
 	void __iomem *mmio = uc_priv->mmio_base;
@@ -379,11 +353,7 @@ static void ahci_print_info(struct ahci_uc_priv *uc_priv)
 #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
 	scc_s = "SATA";
 #else
-# ifdef CONFIG_DM_PCI
 	dm_pci_read_config16(dev, 0x0a, &cc);
-# else
-	pci_read_config_word(pdev, 0x0a, &cc);
-# endif
 	if (cc == 0x0101)
 		scc_s = "IDE";
 	else if (cc == 0x0106)
@@ -428,11 +398,7 @@ static void ahci_print_info(struct ahci_uc_priv *uc_priv)
 }
 
 #if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
-# if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
 static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
-# else
-static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
-# endif
 {
 #if !defined(CONFIG_DM_SCSI)
 	u16 vendor;
@@ -450,7 +416,6 @@ static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
 	uc_priv->udma_mask = 0x7f;	/*Fixme,assume to support UDMA6 */
 
 #if !defined(CONFIG_DM_SCSI)
-#ifdef CONFIG_DM_PCI
 	uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
 					      PCI_REGION_MEM);
 
@@ -462,18 +427,6 @@ static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
 	if (vendor == 0x197b)
 		dm_pci_write_config8(dev, 0x41, 0xa1);
 #else
-	uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
-					   PCI_REGION_MEM);
-
-	/* Take from kernel:
-	 * JMicron-specific fixup:
-	 * make sure we're in AHCI mode
-	 */
-	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
-	if (vendor == 0x197b)
-		pci_write_config_byte(dev, 0x41, 0xa1);
-#endif
-#else
 	struct scsi_plat *plat = dev_get_uclass_plat(dev);
 	uc_priv->mmio_base = (void *)plat->base;
 #endif
@@ -1006,7 +959,6 @@ void scsi_low_level_init(int busdevfunc)
 		return;
 	}
 	uc_priv = probe_ent;
-# if defined(CONFIG_DM_PCI)
 	struct udevice *dev;
 	int ret;
 
@@ -1014,9 +966,6 @@ void scsi_low_level_init(int busdevfunc)
 	if (ret)
 		return;
 	ahci_init_one(uc_priv, dev);
-# else
-	ahci_init_one(uc_priv, busdevfunc);
-# endif
 #else
 	uc_priv = probe_ent;
 #endif
@@ -1026,7 +975,6 @@ void scsi_low_level_init(int busdevfunc)
 #endif
 
 #ifndef CONFIG_SCSI_AHCI_PLAT
-# if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
 int ahci_init_one_dm(struct udevice *dev)
 {
 	struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
@@ -1034,7 +982,6 @@ int ahci_init_one_dm(struct udevice *dev)
 	return ahci_init_one(uc_priv, dev);
 }
 #endif
-#endif
 
 int ahci_start_ports_dm(struct udevice *dev)
 {
@@ -1196,7 +1143,6 @@ int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
 	return 0;
 }
 
-#ifdef CONFIG_DM_PCI
 int ahci_probe_scsi_pci(struct udevice *ahci_dev)
 {
 	ulong base;
@@ -1221,7 +1167,6 @@ int ahci_probe_scsi_pci(struct udevice *ahci_dev)
 						 PCI_REGION_MEM);
 	return ahci_probe_scsi(ahci_dev, base);
 }
-#endif
 
 struct scsi_ops scsi_ops = {
 	.exec		= ahci_scsi_exec,
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index dadb2c7c2e..003222d47b 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -1068,6 +1068,7 @@ static int sata_mv_probe(struct udevice *dev)
 	int nr_ports;
 	int ret;
 	int i;
+	int status = -ENODEV; /* If the probe fails to detected any SATA port */
 
 	/* Get number of ports of this SATA controller */
 	nr_ports = min(fdtdec_get_int(blob, node, "nr-ports", -1),
@@ -1078,7 +1079,7 @@ static int sata_mv_probe(struct udevice *dev)
 					 IF_TYPE_SATA, -1, 512, 0, &blk);
 		if (ret) {
 			debug("Can't create device\n");
-			return ret;
+			continue;
 		}
 
 		priv = dev_get_plat(blk);
@@ -1088,18 +1089,23 @@ static int sata_mv_probe(struct udevice *dev)
 		ret = sata_mv_init_sata(blk, i);
 		if (ret) {
 			debug("%s: Failed to init bus\n", __func__);
-			return ret;
+			continue;
 		}
 
 		/* Scan SATA port */
 		ret = sata_mv_scan_sata(blk, i);
 		if (ret) {
 			debug("%s: Failed to scan bus\n", __func__);
-			return ret;
+			continue;
 		}
+
+		/* If we got here, the current SATA port was probed
+		 * successfully, so set the probe status to successful.
+		 */
+		status = 0;
 	}
 
-	return 0;
+	return status;
 }
 
 static int sata_mv_scan(struct udevice *dev)
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 1e452ad6d9..40f41a817c 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -39,4 +39,11 @@ config NCORE_CACHE
 	  controller. The driver initializes cache directories and coherent
 	  agent interfaces.
 
+config SIFIVE_CCACHE
+	bool "SiFive composable cache"
+	select CACHE
+	help
+	  This driver is for SiFive Composable L2/L3 cache. It enables cache
+	  ways of composable cache.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index fed50be3f9..ad765774e3 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
 obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
 obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
+obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
diff --git a/drivers/cache/cache-sifive-ccache.c b/drivers/cache/cache-sifive-ccache.c
new file mode 100644
index 0000000000..76c0ab26ae
--- /dev/null
+++ b/drivers/cache/cache-sifive-ccache.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 SiFive
+ */
+
+#include <common.h>
+#include <cache.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dm/device.h>
+#include <linux/bitfield.h>
+
+#define SIFIVE_CCACHE_CONFIG		0x000
+#define SIFIVE_CCACHE_CONFIG_WAYS	GENMASK(15, 8)
+
+#define SIFIVE_CCACHE_WAY_ENABLE	0x008
+
+struct sifive_ccache {
+	void __iomem *base;
+};
+
+static int sifive_ccache_enable(struct udevice *dev)
+{
+	struct sifive_ccache *priv = dev_get_priv(dev);
+	u32 config;
+	u32 ways;
+
+	/* Enable all ways of composable cache */
+	config = readl(priv->base + SIFIVE_CCACHE_CONFIG);
+	ways = FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS, config);
+
+	writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE);
+
+	return 0;
+}
+
+static int sifive_ccache_get_info(struct udevice *dev, struct cache_info *info)
+{
+	struct sifive_ccache *priv = dev_get_priv(dev);
+
+	info->base = (phys_addr_t)priv->base;
+
+	return 0;
+}
+
+static const struct cache_ops sifive_ccache_ops = {
+	.enable = sifive_ccache_enable,
+	.get_info = sifive_ccache_get_info,
+};
+
+static int sifive_ccache_probe(struct udevice *dev)
+{
+	struct sifive_ccache *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base)
+		return -EINVAL;
+
+	return 0;
+}
+
+static const struct udevice_id sifive_ccache_ids[] = {
+	{ .compatible = "sifive,fu540-c000-ccache" },
+	{ .compatible = "sifive,fu740-c000-ccache" },
+	{}
+};
+
+U_BOOT_DRIVER(sifive_ccache) = {
+	.name = "sifive_ccache",
+	.id = UCLASS_CACHE,
+	.of_match = sifive_ccache_ids,
+	.probe = sifive_ccache_probe,
+	.priv_auto = sizeof(struct sifive_ccache),
+	.ops = &sifive_ccache_ops,
+};
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 1f5dfb94bb..94ff540111 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -1,6 +1,8 @@
 config FSL_CAAM
 	bool "Freescale Crypto Driver Support"
 	select SHA_HW_ACCEL
+	# hw_sha1() under drivers/crypto, and needed with SHA_HW_ACCEL
+	imply SPL_CRYPTO if (ARM && SPL)
 	imply CMD_HASH
 	help
 	  Enables the Freescale's Cryptographic Accelerator and Assurance
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index afb4c69529..f0439e2417 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -360,7 +360,7 @@ config PIC32_GPIO
 
 config OCTEON_GPIO
 	bool "Octeon II/III/TX/TX2 GPIO driver"
-	depends on DM_GPIO && DM_PCI &&	(ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2)
+	depends on DM_GPIO && PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2)
 	default y
 	help
 	  Add support for the Marvell Octeon GPIO driver. This is used with
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 3a7ecd9274..67841bf3e0 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -18,7 +18,7 @@ obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
 obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o
 obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
 obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
-ifdef CONFIG_DM_PCI
+ifdef CONFIG_PCI
 obj-$(CONFIG_SYS_I2C_DW) += designware_i2c_pci.o
 endif
 obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
diff --git a/drivers/i2c/ocores_i2c.c b/drivers/i2c/ocores_i2c.c
index 088ba9a6a3..f129ec3818 100644
--- a/drivers/i2c/ocores_i2c.c
+++ b/drivers/i2c/ocores_i2c.c
@@ -626,6 +626,7 @@ static const struct udevice_id ocores_i2c_ids[] = {
 { .compatible = "aeroflexgaisler,i2cmst", .data = TYPE_GRLIB },
 { .compatible = "sifive,fu540-c000-i2c" },
 { .compatible = "sifive,i2c0" },
+{ }
 };
 
 U_BOOT_DRIVER(i2c_ocores) = {
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 1d98fa65c4..ebb307e950 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -361,13 +361,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
 		;
 
-	/* Wait at least 8 SD clock cycles before the next command */
-	/*
-	 * Note: This is way more than 8 cycles, but 1ms seems to
-	 * resolve timing issues with some cards
-	 */
-	udelay(1000);
-
 	/* Set up for a data transfer if we have one */
 	if (data) {
 		err = esdhc_setup_data(priv, mmc, data);
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 0e13238c7e..3ee92d03ca 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -342,6 +342,9 @@ void mmc_do_preinit(void)
 
 		if (!m)
 			continue;
+
+		m->user_speed_mode = MMC_MODES_END;  /* Initialising user set speed mode */
+
 		if (m->preinit)
 			mmc_start_init(m);
 	}
@@ -414,7 +417,7 @@ int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg)
 	/* setup initial part type */
 	bdesc->part_type = cfg->part_type;
 	mmc->dev = dev;
-
+	mmc->user_speed_mode = MMC_MODES_END;
 	return 0;
 }
 
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 8078a89f18..d3babbfeb1 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -823,7 +823,7 @@ static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
 	 * capable of polling by using mmc_wait_dat0, then rely on waiting the
 	 * stated timeout to be sufficient.
 	 */
-	if (ret == -ENOSYS && !send_status) {
+	if (ret == -ENOSYS || !send_status) {
 		mdelay(timeout_ms);
 		return 0;
 	}
@@ -2092,14 +2092,16 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
 	}
 
 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
-    CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+    CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
+    CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 	/*
 	 * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
 	 * before doing anything else, since a transition from either of
 	 * the HS200/HS400 mode directly to legacy mode is not supported.
 	 */
 	if (mmc->selected_mode == MMC_HS_200 ||
-	    mmc->selected_mode == MMC_HS_400)
+	    mmc->selected_mode == MMC_HS_400 ||
+	    mmc->selected_mode == MMC_HS_400_ES)
 		mmc_set_card_speed(mmc, MMC_HS, true);
 	else
 #endif
@@ -2862,7 +2864,25 @@ int mmc_start_init(struct mmc *mmc)
 	 * timings.
 	 */
 	mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(MMC_LEGACY) |
-			 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
+			 MMC_MODE_1BIT;
+
+	if (IS_ENABLED(CONFIG_MMC_SPEED_MODE_SET)) {
+		if (mmc->user_speed_mode != MMC_MODES_END) {
+			int i;
+			/* set host caps */
+			if (mmc->host_caps & MMC_CAP(mmc->user_speed_mode)) {
+				/* Remove all existing speed capabilities */
+				for (i = MMC_LEGACY; i < MMC_MODES_END; i++)
+					mmc->host_caps &= ~MMC_CAP(i);
+				mmc->host_caps |= (MMC_CAP(mmc->user_speed_mode)
+						   | MMC_CAP(MMC_LEGACY) |
+						   MMC_MODE_1BIT);
+			} else {
+				pr_err("bus_mode requested is not supported\n");
+				return -EINVAL;
+			}
+		}
+	}
 #if CONFIG_IS_ENABLED(DM_MMC)
 	mmc_deferred_probe(mmc);
 #endif
@@ -2952,7 +2972,7 @@ int mmc_deinit(struct mmc *mmc)
 		return sd_select_mode_and_width(mmc, caps_filtered);
 	} else {
 		caps_filtered = mmc->card_caps &
-			~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400));
+			~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400) | MMC_CAP(MMC_HS_400_ES));
 
 		return mmc_select_mode_and_width(mmc, caps_filtered);
 	}
@@ -3060,6 +3080,8 @@ int mmc_init_device(int num)
 	}
 
 	m = mmc_get_mmc_dev(dev);
+	m->user_speed_mode = MMC_MODES_END; /* Initialising user set speed mode */
+
 	if (!m)
 		return 0;
 	if (m->preinit)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 2f78da61be..03bfd9d18a 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -258,8 +258,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 		flags = SDHCI_CMD_RESP_LONG;
 	else if (cmd->resp_type & MMC_RSP_BUSY) {
 		flags = SDHCI_CMD_RESP_SHORT_BUSY;
-		if (data)
-			mask |= SDHCI_INT_DATA_END;
+		mask |= SDHCI_INT_DATA_END;
 	} else
 		flags = SDHCI_CMD_RESP_SHORT;
 
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 178b8cf106..aaab0cf866 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -349,10 +349,14 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
 		 * register without checking the status register after every
 		 * read. That saves half of the costly MMIO reads, effectively
 		 * doubling the read performance.
+		 * Some SoCs (A20) report a level of 0 if the FIFO is
+		 * completely full (value masked out?). Use a safe minimal
+		 * FIFO size in this case.
 		 */
-		for (in_fifo = SUNXI_MMC_STATUS_FIFO_LEVEL(status);
-		     in_fifo > 0;
-		     in_fifo--)
+		in_fifo = SUNXI_MMC_STATUS_FIFO_LEVEL(status);
+		if (in_fifo == 0 && (status & SUNXI_MMC_STATUS_FIFO_FULL))
+			in_fifo = 32;
+		for (; in_fifo > 0; in_fifo--)
 			buff[i++] = readl_relaxed(&priv->reg->fifo);
 		dmb();
 	}
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 8b1add19e8..6c12959f37 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -225,7 +225,6 @@ config DWC_ETH_QOS_TEGRA186
 
 config E1000
 	bool "Intel PRO/1000 Gigabit Ethernet support"
-	depends on (DM_ETH && DM_PCI) || !DM_ETH
 	help
 	  This driver supports Intel(R) PRO/1000 gigabit ethernet family of
 	  adapters.  For more information on how to identify your adapter, go
@@ -509,7 +508,7 @@ config OCTEONTX2_CGX_INTF
 
 config PCH_GBE
 	bool "Intel Platform Controller Hub EG20T GMAC driver"
-	depends on DM_ETH && DM_PCI
+	depends on DM_ETH
 	select PHYLIB
 	help
 	  This MAC is present in Intel Platform Controller Hub EG20T. It
@@ -608,7 +607,6 @@ source "drivers/net/ti/Kconfig"
 
 config TULIP
 	bool "DEC Tulip DC2114x Ethernet support"
-	depends on (DM_ETH && DM_PCI) || !DM_ETH
 	help
 	  This driver supports DEC DC2114x Fast ethernet chips.
 
@@ -791,7 +789,7 @@ config HIGMACV300_ETH
 
 config FSL_ENETC
 	bool "NXP ENETC Ethernet controller"
-	depends on DM_PCI && DM_ETH && DM_MDIO
+	depends on DM_ETH && DM_MDIO
 	help
 	  This driver supports the NXP ENETC Ethernet controller found on some
 	  of the NXP SoCs.
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 5d92257e74..5aaac603a0 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -756,16 +756,16 @@ int designware_eth_write_hwaddr(struct udevice *dev)
 
 static int designware_eth_bind(struct udevice *dev)
 {
-#ifdef CONFIG_DM_PCI
-	static int num_cards;
-	char name[20];
-
-	/* Create a unique device name for PCI type devices */
-	if (device_is_on_pci_bus(dev)) {
-		sprintf(name, "eth_designware#%u", num_cards++);
-		device_set_name(dev, name);
+	if (IS_ENABLED(CONFIG_PCI)) {
+		static int num_cards;
+		char name[20];
+
+		/* Create a unique device name for PCI type devices */
+		if (device_is_on_pci_bus(dev)) {
+			sprintf(name, "eth_designware#%u", num_cards++);
+			device_set_name(dev, name);
+		}
 	}
-#endif
 
 	return 0;
 }
@@ -831,12 +831,11 @@ int designware_eth_probe(struct udevice *dev)
 	else
 		reset_deassert_bulk(&reset_bulk);
 
-#ifdef CONFIG_DM_PCI
 	/*
 	 * If we are on PCI bus, either directly attached to a PCI root port,
 	 * or via a PCI bridge, fill in plat before we probe the hardware.
 	 */
-	if (device_is_on_pci_bus(dev)) {
+	if (IS_ENABLED(CONFIG_PCI) && device_is_on_pci_bus(dev)) {
 		dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
 		iobase &= PCI_BASE_ADDRESS_MEM_MASK;
 		iobase = dm_pci_mem_to_phys(dev, iobase);
@@ -844,7 +843,6 @@ int designware_eth_probe(struct udevice *dev)
 		pdata->iobase = iobase;
 		pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
 	}
-#endif
 
 	debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
 	ioaddr = iobase;
diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig
index ccf7822dbe..930d2ef113 100644
--- a/drivers/net/mscc_eswitch/Kconfig
+++ b/drivers/net/mscc_eswitch/Kconfig
@@ -39,7 +39,7 @@ config MSCC_SERVAL_SWITCH
 
 config MSCC_FELIX_SWITCH
 	bool "Felix switch driver"
-	depends on DM_DSA && DM_PCI
+	depends on DM_DSA
 	select FSL_ENETC
 	help
 	  This driver supports the Ethernet switch integrated in the
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 97d0de5b11..e93518ebc1 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -2,28 +2,20 @@ menuconfig PCI
 	bool "PCI support"
 	depends on DM
 	default y if PPC
-	select DM_PCI
 	help
 	  Enable support for PCI (Peripheral Interconnect Bus), a type of bus
 	  used on some devices to allow the CPU to communicate with its
 	  peripherals.
 
-config DM_PCI
-	bool
-	help
-	  Use driver model for PCI. Driver model is the new method for
-	  orgnising devices in U-Boot. For PCI, driver model keeps track of
-	  available PCI devices, allows scanning of PCI buses and provides
-	  device configuration support.
+	  This subsystem requires driver model.
 
 if PCI
 
 config DM_PCI_COMPAT
 	bool "Enable compatible functions for PCI"
-	depends on DM_PCI
 	help
 	  Enable compatibility functions for PCI so that old code can be used
-	  with CONFIG_DM_PCI enabled. This should be used as an interim
+	  with CONFIG_PCI enabled. This should be used as an interim
 	  measure when porting a board to use driver model for PCI. Once the
 	  board is fully supported, this option should be disabled.
 
@@ -39,7 +31,6 @@ config PCI_AARDVARK
 
 config PCI_PNP
 	bool "Enable Plug & Play support for PCI"
-	depends on PCI || DM_PCI
 	default y
 	help
 	  Enable PCI memory and I/O space resource allocation and assignment.
@@ -55,7 +46,6 @@ config PCI_REGION_MULTI_ENTRY
 
 config PCI_MAP_SYSTEM_MEMORY
 	bool "Map local system memory from a virtual base address"
-	depends on PCI || DM_PCI
 	depends on MIPS
 	help
 	  Say Y if base address of system memory is being used as a virtual address
@@ -102,14 +92,12 @@ config PCIE_ECAM_SYNQUACER
 
 config PCI_PHYTIUM
 	bool "Phytium PCIe support"
-	depends on DM_PCI
 	help
 	  Say Y here if you want to enable PCIe controller support on
 	  Phytium SoCs.
 
 config PCIE_DW_MVEBU
 	bool "Enable Armada-8K PCIe driver (DesignWare core)"
-	depends on DM_PCI
 	depends on ARMADA_8K
 	help
 	  Say Y here if you want to enable PCIe controller support on
@@ -128,7 +116,6 @@ config PCIE_DW_SIFIVE
 
 config PCIE_FSL
 	bool "FSL PowerPC PCIe support"
-	depends on DM_PCI
 	help
 	  Say Y here if you want to enable PCIe controller support on FSL
 	  PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.
@@ -136,14 +123,12 @@ config PCIE_FSL
 
 config PCI_MPC85XX
 	bool "MPC85XX PowerPC PCI support"
-	depends on DM_PCI
 	help
 	  Say Y here if you want to enable PCI controller support on FSL
 	  PowerPC MPC85xx SoC.
 
 config PCI_RCAR_GEN2
 	bool "Renesas RCar Gen2 PCIe driver"
-	depends on DM_PCI
 	depends on RCAR_32
 	help
 	  Say Y here if you want to enable PCIe controller support on
@@ -152,7 +137,6 @@ config PCI_RCAR_GEN2
 
 config PCI_RCAR_GEN3
 	bool "Renesas RCar Gen3 PCIe driver"
-	depends on DM_PCI
 	depends on RCAR_GEN3
 	help
 	  Say Y here if you want to enable PCIe controller support on
@@ -160,7 +144,7 @@ config PCI_RCAR_GEN3
 
 config PCI_SANDBOX
 	bool "Sandbox PCI support"
-	depends on SANDBOX && DM_PCI
+	depends on SANDBOX
 	help
 	  Support PCI on sandbox, as an emulated bus. This permits testing of
 	  PCI feature such as bus scanning, device configuration and device
@@ -195,7 +179,6 @@ config PCIE_OCTEON
 
 config PCI_XILINX
 	bool "Xilinx AXI Bridge for PCI Express"
-	depends on DM_PCI
 	help
 	  Enable support for the Xilinx AXI bridge for PCI express, an IP block
 	  which can be used on some generations of Xilinx FPGAs.
@@ -205,7 +188,6 @@ config PCIE_LAYERSCAPE
 
 config PCIE_LAYERSCAPE_RC
 	bool "Layerscape PCIe Root Complex mode support"
-	depends on DM_PCI
 	select PCIE_LAYERSCAPE
 	help
 	  Enable Layerscape PCIe Root Complex mode driver support. The Layerscape
@@ -227,7 +209,6 @@ config PCI_IOMMU_EXTRA_MAPPINGS
 
 config PCIE_LAYERSCAPE_EP
 	bool "Layerscape PCIe Endpoint mode support"
-	depends on DM_PCI
 	select PCIE_LAYERSCAPE
 	select PCI_ENDPOINT
 	help
@@ -238,7 +219,6 @@ config PCIE_LAYERSCAPE_EP
 
 config PCIE_LAYERSCAPE_GEN4
 	bool "Layerscape Gen4 PCIe support"
-	depends on DM_PCI
 	help
 	  Support PCIe Gen4 on NXP Layerscape SoCs, which may have one or
 	  several PCIe controllers. The PCIe controller can work in RC or
@@ -271,14 +251,12 @@ config FSL_PCIE_EP_COMPAT
 
 config PCIE_INTEL_FPGA
 	bool "Intel FPGA PCIe support"
-	depends on DM_PCI
 	help
 	  Say Y here if you want to enable PCIe controller support on Intel
 	  FPGA, example Stratix 10.
 
 config PCIE_IPROC
 	bool "Iproc PCIe support"
-	depends on DM_PCI
 	help
 	  Broadcom iProc PCIe controller driver.
 	  Say Y here if you want to enable Broadcom iProc PCIe controller,
@@ -286,7 +264,6 @@ config PCIE_IPROC
 config PCI_MVEBU
 	bool "Enable Armada XP/38x PCIe driver"
 	depends on ARCH_MVEBU
-	select DM_PCI
 	select MISC
 	help
 	  Say Y here if you want to enable PCIe controller support on
@@ -294,7 +271,6 @@ config PCI_MVEBU
 
 config PCIE_DW_COMMON
 	bool
-	select DM_PCI
 
 config PCI_KEYSTONE
 	bool "TI Keystone PCIe controller"
@@ -304,7 +280,6 @@ config PCI_KEYSTONE
 
 config PCIE_MEDIATEK
 	bool "MediaTek PCIe Gen2 controller"
-	depends on DM_PCI
 	depends on ARCH_MEDIATEK
 	help
 	  Say Y here if you want to enable Gen2 PCIe controller,
@@ -321,7 +296,6 @@ config PCIE_DW_MESON
 config PCIE_ROCKCHIP
 	bool "Enable Rockchip PCIe driver"
 	depends on ARCH_ROCKCHIP
-	select DM_PCI
 	select PHY_ROCKCHIP_PCIE
 	default y if ROCKCHIP_RK3399
 	help
@@ -339,7 +313,6 @@ config PCIE_DW_ROCKCHIP
 
 config PCI_BRCMSTB
 	bool "Broadcom STB PCIe controller"
-	depends on DM_PCI
 	depends on ARCH_BCM283X
 	help
 	  Say Y here if you want to enable support for PCIe controller
@@ -349,7 +322,6 @@ config PCI_BRCMSTB
 
 config PCIE_UNIPHIER
 	bool "Socionext UniPhier PCIe driver"
-	depends on DM_PCI
 	depends on ARCH_UNIPHIER
 	select PHY_UNIPHIER_PCIE
 	help
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index bdfdec98a0..4a131bf5ca 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o
 obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
 obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o
 obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
-obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
 obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
 obj-$(CONFIG_PCI_MPC85XX) += pci_mpc85xx.o
 obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 815b26162f..cf6e30f936 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -234,19 +234,19 @@ static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
  *
  * Wait up to 1.5 seconds for PIO access to be accomplished.
  *
- * Return 1 (true) if PIO access is accomplished.
- * Return 0 (false) if PIO access is timed out.
+ * Return positive - retry count if PIO access is accomplished.
+ * Return negative - error if PIO access is timed out.
  */
 static int pcie_advk_wait_pio(struct pcie_advk *pcie)
 {
 	uint start, isr;
 	uint count;
 
-	for (count = 0; count < PIO_MAX_RETRIES; count++) {
+	for (count = 1; count <= PIO_MAX_RETRIES; count++) {
 		start = advk_readl(pcie, PIO_START);
 		isr = advk_readl(pcie, PIO_ISR);
 		if (!start && isr)
-			return 1;
+			return count;
 		/*
 		 * Do not check the PIO state too frequently,
 		 * 100us delay is appropriate.
@@ -255,7 +255,7 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie)
 	}
 
 	dev_err(pcie->dev, "PIO read/write transfer time out\n");
-	return 0;
+	return -ETIMEDOUT;
 }
 
 /**
@@ -265,11 +265,13 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie)
  * @allow_crs: Only for read requests, if CRS response is allowed
  * @read_val: Pointer to the read result
  *
+ * Return: 0 on success
  */
 static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
 				      bool allow_crs,
 				      uint *read_val)
 {
+	int ret;
 	uint reg;
 	unsigned int status;
 	char *strcomp_status, *str_posted;
@@ -282,6 +284,7 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
 	case PIO_COMPLETION_STATUS_OK:
 		if (reg & PIO_ERR_STATUS) {
 			strcomp_status = "COMP_ERR";
+			ret = -EFAULT;
 			break;
 		}
 		/* Get the read result */
@@ -289,40 +292,46 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
 			*read_val = advk_readl(pcie, PIO_RD_DATA);
 		/* No error */
 		strcomp_status = NULL;
+		ret = 0;
 		break;
 	case PIO_COMPLETION_STATUS_UR:
 		strcomp_status = "UR";
+		ret = -EOPNOTSUPP;
 		break;
 	case PIO_COMPLETION_STATUS_CRS:
 		if (allow_crs && read_val) {
 			/* For reading, CRS is not an error status. */
 			*read_val = CFG_RD_CRS_VAL;
 			strcomp_status = NULL;
+			ret = 0;
 		} else {
 			strcomp_status = "CRS";
+			ret = -EAGAIN;
 		}
 		break;
 	case PIO_COMPLETION_STATUS_CA:
 		strcomp_status = "CA";
+		ret = -ECANCELED;
 		break;
 	default:
 		strcomp_status = "Unknown";
+		ret = -EINVAL;
 		break;
 	}
 
 	if (!strcomp_status)
-		return 0;
+		return ret;
 
 	if (reg & PIO_NON_POSTED_REQ)
 		str_posted = "Non-posted";
 	else
 		str_posted = "Posted";
 
-	dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
+	dev_dbg(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
 		str_posted, strcomp_status, reg,
 		advk_readl(pcie, PIO_ADDR_LS));
 
-	return -EFAULT;
+	return ret;
 }
 
 /**
@@ -345,6 +354,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
 				 enum pci_size_t size)
 {
 	struct pcie_advk *pcie = dev_get_priv(bus);
+	int retry_count;
 	bool allow_crs;
 	uint reg;
 	int ret;
@@ -358,7 +368,18 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
 		return 0;
 	}
 
-	allow_crs = (offset == PCI_VENDOR_ID) && (size == 4);
+	/*
+	 * Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to
+	 * OS is allowed only for 4-byte PCI_VENDOR_ID config read request and
+	 * only when CRSSVE bit in Root Port PCIe device is enabled. In all
+	 * other error PCIe Root Complex must return all-ones.
+	 * Aardvark HW does not have Root Port PCIe device and U-Boot does not
+	 * implement emulation of this device.
+	 * U-Boot currently does not support handling of CRS return value for
+	 * PCI_VENDOR_ID config read request and also does not set CRSSVE bit.
+	 * Therefore disable returning CRS response for now.
+	 */
+	allow_crs = false;
 
 	if (advk_readl(pcie, PIO_START)) {
 		dev_err(pcie->dev,
@@ -368,7 +389,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
 			return 0;
 		}
 		*valuep = pci_get_ff(size);
-		return -EINVAL;
+		return -EAGAIN;
 	}
 
 	/* Program the control register */
@@ -385,21 +406,29 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
 	advk_writel(pcie, reg, PIO_ADDR_LS);
 	advk_writel(pcie, 0, PIO_ADDR_MS);
 
+	retry_count = 0;
+
+retry:
 	/* Start the transfer */
 	advk_writel(pcie, 1, PIO_ISR);
 	advk_writel(pcie, 1, PIO_START);
 
-	if (!pcie_advk_wait_pio(pcie)) {
+	ret = pcie_advk_wait_pio(pcie);
+	if (ret < 0) {
 		if (allow_crs) {
 			*valuep = CFG_RD_CRS_VAL;
 			return 0;
 		}
 		*valuep = pci_get_ff(size);
-		return -EINVAL;
+		return ret;
 	}
 
+	retry_count += ret;
+
 	/* Check PIO status and get the read result */
 	ret = pcie_advk_check_pio_status(pcie, allow_crs, &reg);
+	if (ret == -EAGAIN && retry_count < PIO_MAX_RETRIES)
+		goto retry;
 	if (ret) {
 		*valuep = pci_get_ff(size);
 		return ret;
@@ -461,7 +490,9 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
 				  enum pci_size_t size)
 {
 	struct pcie_advk *pcie = dev_get_priv(bus);
+	int retry_count;
 	uint reg;
+	int ret;
 
 	dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
 		PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
@@ -476,7 +507,7 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
 	if (advk_readl(pcie, PIO_START)) {
 		dev_err(pcie->dev,
 			"Previous PIO read/write transfer is still running\n");
-		return -EINVAL;
+		return -EAGAIN;
 	}
 
 	/* Program the control register */
@@ -504,16 +535,24 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
 	advk_writel(pcie, reg, PIO_WR_DATA_STRB);
 	dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
 
+	retry_count = 0;
+
+retry:
 	/* Start the transfer */
 	advk_writel(pcie, 1, PIO_ISR);
 	advk_writel(pcie, 1, PIO_START);
 
-	if (!pcie_advk_wait_pio(pcie)) {
-		return -EINVAL;
-	}
+	ret = pcie_advk_wait_pio(pcie);
+	if (ret < 0)
+		return ret;
+
+	retry_count += ret;
 
 	/* Check PIO status */
-	return pcie_advk_check_pio_status(pcie, false, NULL);
+	ret = pcie_advk_check_pio_status(pcie, false, NULL);
+	if (ret == -EAGAIN && retry_count < PIO_MAX_RETRIES)
+		goto retry;
+	return ret;
 }
 
 /**
diff --git a/drivers/pci/pci_indirect.c b/drivers/pci/pci_indirect.c
deleted file mode 100644
index 6134c22d1b..0000000000
--- a/drivers/pci/pci_indirect.c
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Support for indirect PCI bridges.
- *
- * Copyright (C) 1998 Gabriel Paubert.
- */
-
-#include <common.h>
-
-#if !defined(__I386__) && !defined(CONFIG_DM_PCI)
-
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <pci.h>
-
-#define cfg_read(val, addr, type, op)	*val = op((type)(addr))
-#define cfg_write(val, addr, type, op)	op((type *)(addr), (val))
-
-#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
-#define INDIRECT_PCI_OP(rw, size, type, op, mask)                        \
-static int                                                               \
-indirect_##rw##_config_##size(struct pci_controller *hose,               \
-			      pci_dev_t dev, int offset, type val)       \
-{                                                                        \
-	u32 b, d,f;							 \
-	b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev);		 \
-	b = b - hose->first_busno;					 \
-	dev = PCI_BDF(b, d, f);						 \
-	*(hose->cfg_addr) = dev | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; \
-	sync();                                                          \
-	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
-	return 0;                                                        \
-}
-#else
-#define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
-static int								 \
-indirect_##rw##_config_##size(struct pci_controller *hose,		 \
-			      pci_dev_t dev, int offset, type val)	 \
-{									 \
-	u32 b, d,f;							 \
-	b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev);		 \
-	b = b - hose->first_busno;					 \
-	dev = PCI_BDF(b, d, f);						 \
-	out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);	 \
-	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	 \
-	return 0;							 \
-}
-#endif
-
-INDIRECT_PCI_OP(read, byte, u8 *, in_8, 3)
-INDIRECT_PCI_OP(read, word, u16 *, in_le16, 2)
-INDIRECT_PCI_OP(read, dword, u32 *, in_le32, 0)
-INDIRECT_PCI_OP(write, byte, u8, out_8, 3)
-INDIRECT_PCI_OP(write, word, u16, out_le16, 2)
-INDIRECT_PCI_OP(write, dword, u32, out_le32, 0)
-
-void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
-{
-	pci_set_ops(hose,
-		    indirect_read_config_byte,
-		    indirect_read_config_word,
-		    indirect_read_config_dword,
-		    indirect_write_config_byte,
-		    indirect_write_config_word,
-		    indirect_write_config_dword);
-
-	hose->cfg_addr = (unsigned int *) cfg_addr;
-	hose->cfg_data = (unsigned char *) cfg_data;
-}
-
-#endif	/* !__I386__ */
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 77fb851114..30eaa376c8 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -69,7 +69,7 @@ config PINCONF_RECURSIVE
 	  direct children of the pin controller device (may be grandchildren for
 	  example). It is define is each individual pin controller device.
 	  Say Y here if you want to keep this behavior with the pinconfig
-	  u-class: all sub are recursivelly bounded.
+	  u-class: all sub are recursively bounded.
 	  If the option is disabled, this behavior is deactivated and only
 	  the direct children of pin controller will be assumed as pin
 	  configuration; you can save memory footprint when this feature is
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index e12699bec7..d07e9a28af 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -271,7 +271,7 @@ config NXP_FSPI
 
 config OCTEON_SPI
 	bool "Octeon SPI driver"
-	depends on DM_PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2)
+	depends on ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2
 	help
 	  Enable the Octeon SPI driver. This driver can be used to
 	  access the SPI NOR flash on Octeon II/III and OcteonTX/TX2
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index fc81b07343..2db4ae20f1 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -77,6 +77,7 @@
 
 #define GQSPI_GFIFO_SELECT		BIT(0)
 #define GQSPI_FIFO_THRESHOLD		1
+#define GQSPI_GENFIFO_THRESHOLD		31
 
 #define SPI_XFER_ON_BOTH		0
 #define SPI_XFER_ON_LOWER		1
@@ -197,14 +198,15 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
 	writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->idisr);
 	writel(GQSPI_FIFO_THRESHOLD, &regs->txftr);
 	writel(GQSPI_FIFO_THRESHOLD, &regs->rxftr);
+	writel(GQSPI_GENFIFO_THRESHOLD, &regs->gqfthr);
 	writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->isr);
+	writel(~GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 
 	config_reg = readl(&regs->confr);
 	config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
 			GQSPI_CONFIG_MODE_EN_MASK);
-	config_reg |= GQSPI_CONFIG_DMA_MODE |
-		      GQSPI_GFIFO_WP_HOLD |
-		      GQSPI_DFLT_BAUD_RATE_DIV;
+	config_reg |= GQSPI_CONFIG_DMA_MODE | GQSPI_GFIFO_WP_HOLD |
+		      GQSPI_DFLT_BAUD_RATE_DIV | GQSPI_GFIFO_STRT_MODE_MASK;
 	writel(config_reg, &regs->confr);
 
 	writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
@@ -242,6 +244,8 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
 	u32 config_reg, ier;
 	int ret = 0;
 
+	writel(gqspi_fifo_reg, &regs->genfifo);
+
 	config_reg = readl(&regs->confr);
 	/* Manual start if needed */
 	config_reg |= GQSPI_STRT_GEN_FIFO;
@@ -249,16 +253,15 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
 
 	/* Enable interrupts */
 	ier = readl(&regs->ier);
-	ier |= GQSPI_IXR_GFNFULL_MASK;
+	ier |= GQSPI_IXR_GFEMTY_MASK;
 	writel(ier, &regs->ier);
 
-	/* Wait until the fifo is not full to write the new command */
-	ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFNFULL_MASK, 1,
+	/* Wait until the gen fifo is empty to write the new command */
+	ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFEMTY_MASK, 1,
 				GQSPI_TIMEOUT, 1);
 	if (ret)
 		printf("%s Timeout\n", __func__);
 
-	writel(gqspi_fifo_reg, &regs->genfifo);
 }
 
 static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
@@ -572,25 +575,20 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
 				 u32 gen_fifo_cmd, u32 *buf)
 {
 	u32 addr;
-	u32 size, len;
+	u32 size;
 	u32 actuallen = priv->len;
 	int ret = 0;
 	struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
 
 	writel((unsigned long)buf, &dma_regs->dmadst);
-	writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize);
+	writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize);
 	writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
 	addr = (unsigned long)buf;
-	size = roundup(priv->len, ARCH_DMA_MINALIGN);
+	size = roundup(priv->len, GQSPI_DMA_ALIGN);
 	flush_dcache_range(addr, addr + size);
 
 	while (priv->len) {
-		len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
-		if (!(gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) &&
-		    (len % ARCH_DMA_MINALIGN)) {
-			gen_fifo_cmd &= ~GENMASK(7, 0);
-			gen_fifo_cmd |= roundup(len, ARCH_DMA_MINALIGN);
-		}
+		zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 		zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 
 		debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig
index 1835607083..863c3fbe02 100644
--- a/drivers/virtio/Kconfig
+++ b/drivers/virtio/Kconfig
@@ -31,7 +31,7 @@ config VIRTIO_MMIO
 
 config VIRTIO_PCI
 	bool "PCI driver for virtio devices"
-	depends on DM_PCI
+	depends on PCI
 	select VIRTIO
 	help
 	  This driver provides support for virtio based paravirtual device