diff options
| author | Tom Rini <trini@konsulko.com> | 2021-08-03 04:35:50 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-08-03 04:35:50 +0300 |
| commit | 3b64774323298362f9833aac75bb4639b4f98999 (patch) | |
| tree | 34a6428754d442d5559a7131ff27225ec7c0663a /drivers | |
| parent | 51aef405550e603ff702c034f0e2cd0f15bdf2bb (diff) | |
| parent | 9feb5bdcc07b27806df07fd6b9260bb5cdef072d (diff) | |
| download | u-boot-3b64774323298362f9833aac75bb4639b4f98999.tar.xz | |
Merge https://source.denx.de/u-boot/custodians/u-boot-x86
- Fixed broken ICH SPI driver in software sequencer mode
- Added "m25p,fast-read" to SPI flash node for x86 boards
- Drop ROM_NEEDS_BLOBS and BUILD_ROM for x86 ROM builds
- Define a default TSC timer frequency for all x86 boards
- x86 MTRR MSR programming codes bug fixes
- x86 "hob" command bug fixes
- Don't program MTRR for DRAM for FSP1
- Move INIT_PHASE_END_FIRMWARE to FSP2
- Use external graphics card by default on Intel Crown Bay
- tangier: Fix DMA controller IRQ polarity in CSRT
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/spi/ich.c | 6 | ||||
| -rw-r--r-- | drivers/timer/Kconfig | 8 | ||||
| -rw-r--r-- | drivers/timer/tsc_timer.c | 5 |
3 files changed, 11 insertions, 8 deletions
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 3d49c22a9d..08d54e86f4 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -918,12 +918,14 @@ static int ich_spi_child_pre_probe(struct udevice *dev) struct spi_slave *slave = dev_get_parent_priv(dev); /* - * Yes this controller can only write a small number of bytes at + * Yes this controller can only transfer a small number of bytes at * once! The limit is typically 64 bytes. For hardware sequencing a * a loop is used to get around this. */ - if (!plat->hwseq) + if (!plat->hwseq) { + slave->max_read_size = priv->databytes; slave->max_write_size = priv->databytes; + } /* * ICH 7 SPI controller only supports array read command * and byte program command for SST flash diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index ee81dfa776..8913142654 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -124,12 +124,12 @@ config RENESAS_OSTM_TIMER Enables support for the Renesas OSTM Timer driver. This timer is present on Renesas RZ/A1 R7S72100 SoCs. -config X86_TSC_TIMER_EARLY_FREQ - int "x86 TSC timer frequency in MHz when used as the early timer" +config X86_TSC_TIMER_FREQ + int "x86 TSC timer frequency in Hz" depends on X86_TSC_TIMER - default 1000 + default 1000000000 help - Sets the estimated CPU frequency in MHz when TSC is used as the + Sets the estimated CPU frequency in Hz when TSC is used as the early timer and the frequency can neither be calibrated via some hardware ways, nor got from device tree at the time when device tree is not available yet. diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index 7d19a99622..adef50c374 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -425,12 +425,13 @@ static void tsc_timer_ensure_setup(bool early) goto done; if (early) - fast_calibrate = CONFIG_X86_TSC_TIMER_EARLY_FREQ; + gd->arch.clock_rate = CONFIG_X86_TSC_TIMER_FREQ; else return; done: - gd->arch.clock_rate = fast_calibrate * 1000000; + if (!gd->arch.clock_rate) + gd->arch.clock_rate = fast_calibrate * 1000000; } gd->arch.tsc_inited = true; } |