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authorSimon Glass <sjg@chromium.org>2021-08-02 03:54:29 +0300
committerTom Rini <trini@konsulko.com>2021-08-06 02:46:35 +0300
commit4afab721f15f96152a5a16342c468cbf6e85272c (patch)
tree273e23e75358a4499c5561fa3ff128e3007bcfc5 /drivers
parent0ecc7a0cbf127f426a8ed5a974012d5a1e6d6d34 (diff)
downloadu-boot-4afab721f15f96152a5a16342c468cbf6e85272c.tar.xz
pci: gt64120: Drop use of DM_PCI
Now that DM_PCI is always enabled we don't need to check it. Drop this old code. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pci/pci_gt64120.c64
1 files changed, 0 insertions, 64 deletions
diff --git a/drivers/pci/pci_gt64120.c b/drivers/pci/pci_gt64120.c
index e57fedf036..153c65b119 100644
--- a/drivers/pci/pci_gt64120.c
+++ b/drivers/pci/pci_gt64120.c
@@ -114,69 +114,6 @@ static int gt_config_access(struct gt64120_pci_controller *gt,
return 0;
}
-#if !IS_ENABLED(CONFIG_DM_PCI)
-static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
- int where, u32 *value)
-{
- struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
-
- *value = 0xffffffff;
- return gt_config_access(gt, PCI_ACCESS_READ, dev, where, value);
-}
-
-static int gt_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
- int where, u32 value)
-{
- struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
- u32 data = value;
-
- return gt_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
-}
-
-void gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
- unsigned long sys_size, unsigned long mem_bus,
- unsigned long mem_phys, unsigned long mem_size,
- unsigned long io_bus, unsigned long io_phys,
- unsigned long io_size)
-{
- static struct gt64120_pci_controller global_gt;
- struct gt64120_pci_controller *gt;
- struct pci_controller *hose;
-
- gt = &global_gt;
- gt->regs = regs;
-
- hose = &gt->hose;
-
- hose->first_busno = 0;
- hose->last_busno = 0;
-
- /* System memory space */
- pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI memory space */
- pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
- PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
- PCI_REGION_IO);
-
- hose->region_count = 3;
-
- pci_set_ops(hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- gt_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- gt_write_config_dword);
-
- pci_register_hose(hose);
- hose->last_busno = pci_hose_scan(hose);
-}
-#else
static int gt64120_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
uint where, ulong *val,
enum pci_size_t size)
@@ -246,4 +183,3 @@ U_BOOT_DRIVER(gt64120_pci) = {
.probe = gt64120_pci_probe,
.priv_auto = sizeof(struct gt64120_pci_controller),
};
-#endif