Merge branch '2021-08-30-kconfig-migrations-part1' into next

- Begin merging some Kconfig migration, and CONFIG namespace cleanup series in. This gives us: - A number of I2C symbols migrated over - DWC2, i8042, altera_spi and a few other areas updated to use CFG not CONFIG for the concept of "configuration space" defines. - Rename CONFIG_EXTRA_ENV_BOARD_SETTINGS to EXTRA_ENV_BOARD_SETTINGS - Some dead code removal. - Rename a number of CONFIG symbols that were only referenced within the config header to not use CONFIG as a prefix.
author: Tom Rini <trini@konsulko.com> 2021-08-30 23:44:54 +0300
committer: Tom Rini <trini@konsulko.com> 2021-08-30 23:56:54 +0300
commit: a85a8e63c5cf8ccb3905eb5982bf8bdcb2978557 (patch)
tree: b9feab308105519bdac26729cee734ef49bb62f2 /drivers
parent: 9b0583a839ab8b086b65b4762769abbe048a524d (diff)
parent: 809c4f242f6c05f67a097ace0098c5bc1dfebdfb (diff)
download: u-boot-a85a8e63c5cf8ccb3905eb5982bf8bdcb2978557.tar.xz
24 files changed, 257 insertions, 1877 deletions
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 63d03a3ceb..5d27f503bf 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -47,6 +47,35 @@ config SPL_DM_I2C
 	  device (bus child) info is kept as parent platdata. The interface
 	  is defined in include/i2c.h.
 
+config SYS_I2C_LEGACY
+	bool "Enable legacy I2C subsystem and drivers"
+	depends on !DM_I2C
+	help
+	  Enable the legacy I2C subsystem and drivers.  While this is
+	  deprecated in U-Boot itself, this can be useful in some situations
+	  in SPL or TPL.
+
+config SPL_SYS_I2C_LEGACY
+	bool "Enable legacy I2C subsystem and drivers in SPL"
+	depends on SUPPORT_SPL && !SPL_DM_I2C
+	help
+	  Enable the legacy I2C subsystem and drivers in SPL.  This is useful
+	  in some size constrained situations.
+
+config TPL_SYS_I2C_LEGACY
+	bool "Enable legacy I2C subsystem and drivers in TPL"
+	depends on SUPPORT_TPL && !SPL_DM_I2C
+	help
+	  Enable the legacy I2C subsystem and drivers in TPL.  This is useful
+	  in some size constrained situations.
+
+config SYS_I2C_EARLY_INIT
+	bool "Enable legacy I2C subsystem early in boot"
+	depends on BOARD_EARLY_INIT_F && SPL_SYS_I2C_LEGACY && SYS_I2C_MXC
+	help
+	  Add the function prototype for i2c_early_init_f which is called in
+	  board_early_init_f.
+
 config I2C_CROS_EC_TUNNEL
 	tristate "Chrome OS EC tunnel I2C bus"
 	depends on CROS_EC
@@ -124,11 +153,36 @@ config SYS_I2C_IPROC
 
 config SYS_I2C_FSL
        bool "Freescale I2C bus driver"
-       depends on DM_I2C
        help
 	  Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
 	  MPC85xx processors.
 
+if SYS_I2C_FSL && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
+config SYS_FSL_I2C_OFFSET
+	hex "Offset from the IMMR of the address of the first I2C controller"
+
+config SYS_FSL_HAS_I2C2_OFFSET
+	bool "Support a second I2C controller"
+
+config SYS_FSL_I2C2_OFFSET
+	hex "Offset from the IMMR of the address of the second I2C controller"
+	depends on SYS_FSL_HAS_I2C2_OFFSET
+
+config SYS_FSL_HAS_I2C3_OFFSET
+	bool "Support a third I2C controller"
+
+config SYS_FSL_I2C3_OFFSET
+	hex "Offset from the IMMR of the address of the third I2C controller"
+	depends on SYS_FSL_HAS_I2C3_OFFSET
+
+config SYS_FSL_HAS_I2C4_OFFSET
+	bool "Support a fourth I2C controller"
+
+config SYS_FSL_I2C4_OFFSET
+	hex "Offset from the IMMR of the address of the fourth I2C controller"
+	depends on SYS_FSL_HAS_I2C4_OFFSET
+endif
+
 config SYS_I2C_CADENCE
 	tristate "Cadence I2C Controller"
 	depends on DM_I2C
@@ -205,10 +259,7 @@ config SYS_I2C_MXC
 	  channels and operating on standard mode up to 100 kbits/s and fast
 	  mode up to 400 kbits/s.
 
-# These settings are not used with DM_I2C, however SPL doesn't use
-# DM_I2C even if DM_I2C is enabled, and so might use these settings even
-# when main u-boot does not!
-if SYS_I2C_MXC && (!DM_I2C || SPL)
+if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
 config SYS_I2C_MXC_I2C1
 	bool "NXP MXC I2C1"
 	help
@@ -267,7 +318,7 @@ config SYS_MXC_I2C1_SPEED
 	 MXC I2C Channel 1 speed
 
 config SYS_MXC_I2C1_SLAVE
-	int "I2C1 Slave"
+	hex "I2C1 Slave"
 	default 0
 	help
 	 MXC I2C1 Slave
@@ -282,7 +333,7 @@ config SYS_MXC_I2C2_SPEED
 	 MXC I2C Channel 2 speed
 
 config SYS_MXC_I2C2_SLAVE
-	int "I2C2 Slave"
+	hex "I2C2 Slave"
 	default 0
 	help
 	 MXC I2C2 Slave
@@ -296,7 +347,7 @@ config SYS_MXC_I2C3_SPEED
 	 MXC I2C Channel 3 speed
 
 config SYS_MXC_I2C3_SLAVE
-	int "I2C3 Slave"
+	hex "I2C3 Slave"
 	default 0
 	help
 	 MXC I2C3 Slave
@@ -310,7 +361,7 @@ config SYS_MXC_I2C4_SPEED
 	 MXC I2C Channel 4 speed
 
 config SYS_MXC_I2C4_SLAVE
-	int "I2C4 Slave"
+	hex "I2C4 Slave"
 	default 0
 	help
 	 MXC I2C4 Slave
@@ -324,7 +375,7 @@ config SYS_MXC_I2C5_SPEED
 	 MXC I2C Channel 5 speed
 
 config SYS_MXC_I2C5_SLAVE
-	int "I2C5 Slave"
+	hex "I2C5 Slave"
 	default 0
 	help
 	 MXC I2C5 Slave
@@ -338,7 +389,7 @@ config SYS_MXC_I2C6_SPEED
 	 MXC I2C Channel 6 speed
 
 config SYS_MXC_I2C6_SLAVE
-	int "I2C6 Slave"
+	hex "I2C6 Slave"
 	default 0
 	help
 	 MXC I2C6 Slave
@@ -352,7 +403,7 @@ config SYS_MXC_I2C7_SPEED
 	 MXC I2C Channel 7 speed
 
 config SYS_MXC_I2C7_SLAVE
-	int "I2C7 Slave"
+	hex "I2C7 Slave"
 	default 0
 	help
 	 MXC I2C7 Slave
@@ -366,7 +417,7 @@ config SYS_MXC_I2C8_SPEED
 	 MXC I2C Channel 8 speed
 
 config SYS_MXC_I2C8_SLAVE
-	int "I2C8 Slave"
+	hex "I2C8 Slave"
 	default 0
 	help
 	 MXC I2C8 Slave
@@ -394,20 +445,6 @@ config SYS_I2C_OMAP24XX
 	help
 	  Add support for the OMAP2+ I2C driver.
 
-if SYS_I2C_OMAP24XX
-config SYS_OMAP24_I2C_SLAVE
-	int "I2C Slave addr channel 0"
-	default 1
-	help
-	  OMAP24xx I2C Slave address channel 0
-
-config SYS_OMAP24_I2C_SPEED
-	int "I2C Slave channel 0 speed"
-	default 100000
-	help
-	  OMAP24xx Slave speed channel 0
-endif
-
 config SYS_I2C_RCAR_I2C
 	bool "Renesas RCar I2C driver"
 	depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
@@ -437,6 +474,73 @@ config SYS_I2C_SANDBOX
 	  bus. Devices can be attached to the bus using the device tree
 	  which specifies the driver to use.  See sandbox.dts as an example.
 
+config SYS_I2C_SH
+	bool "Legacy SuperH I2C interface"
+	depends on ARCH_RMOBILE && SYS_I2C_LEGACY
+	help
+	  Enable the legacy SuperH I2C interface.
+
+if SYS_I2C_SH
+config SYS_I2C_SH_NUM_CONTROLLERS
+	int
+	default 5
+
+config SYS_I2C_SH_BASE0
+	hex
+	default 0xE6820000
+
+config SYS_I2C_SH_BASE1
+	hex
+	default 0xE6822000
+
+config SYS_I2C_SH_BASE2
+	hex
+	default 0xE6824000
+
+config SYS_I2C_SH_BASE3
+	hex
+	default 0xE6826000
+
+config SYS_I2C_SH_BASE4
+	hex
+	default 0xE6828000
+
+config SH_I2C_8BIT
+	bool
+	default y
+
+config SH_I2C_DATA_HIGH
+	int
+	default 4
+
+config SH_I2C_DATA_LOW
+	int
+	default 5
+
+config SH_I2C_CLOCK
+	int
+	default 104000000
+endif
+
+config SYS_I2C_SOFT
+	bool "Legacy software I2C interface"
+	help
+	  Enable the legacy software defined I2C interface
+
+config SYS_I2C_SOFT_SPEED
+	int "Software I2C bus speed"
+	depends on SYS_I2C_SOFT
+	default 100000
+	help
+	  Speed of the software I2C bus
+
+config SYS_I2C_SOFT_SLAVE
+	hex "Software I2C slave address"
+	depends on SYS_I2C_SOFT
+	default 0xfe
+	help
+	  Slave address of the software I2C bus
+
 config SYS_I2C_OCTEON
 	bool "Octeon II/III/TX/TX2 I2C driver"
 	depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
@@ -449,7 +553,7 @@ config SYS_I2C_OCTEON
 
 config SYS_I2C_S3C24X0
 	bool "Samsung I2C driver"
-	depends on ARCH_EXYNOS4 && DM_I2C
+	depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C
 	help
 	  Support for Samsung I2C controller as Samsung SoCs.
 
@@ -511,7 +615,6 @@ config SYS_I2C_VERSATILE
 
 config SYS_I2C_MVTWSI
 	bool "Marvell I2C driver"
-	depends on DM_I2C
 	help
 	  Support for Marvell I2C controllers as used on the orion5x and
 	  kirkwood SoC families.
@@ -526,6 +629,25 @@ config TEGRA186_BPMP_I2C
 	  by the BPMP, and can only be accessed by the main CPU via IPC
 	  requests to the BPMP. This driver covers the latter case.
 
+config SYS_I2C_SLAVE
+	hex "I2C Slave address channel (all buses)"
+	depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
+	default 0xfe
+	help
+	  I2C Slave address channel 0 for all buses in the legacy drivers.
+	  Many boards/controllers/drivers don't support an I2C slave
+	  interface so provide a default slave address for them for use in
+	  common code.  A real value for CONFIG_SYS_I2C_SLAVE should be
+	  defined for any board which does support a slave interface and
+	  this default used otherwise.
+
+config SYS_I2C_SPEED
+	int "I2C Slave channel 0 speed (all buses)"
+	depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
+	default 100000
+	help
+	  I2C Slave speed channel 0 for all buses in the legacy drivers.
+
 config SYS_I2C_BUS_MAX
 	int "Max I2C busses"
 	depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index c2eb24e0f7..3a7ecd9274 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -11,7 +11,7 @@ obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
 obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
 
 obj-$(CONFIG_I2C_MV) += mv_i2c.o
-obj-$(CONFIG_SYS_I2C_LEGACY) += i2c_core.o
+obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += i2c_core.o
 obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
 obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
 obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index e57eed0f6c..d95f77649e 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -674,24 +674,6 @@ U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 			 dw_i2c_write, dw_i2c_set_bus_speed,
 			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 
-#if CONFIG_SYS_I2C_BUS_MAX >= 2
-U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
-			 dw_i2c_write, dw_i2c_set_bus_speed,
-			 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
-#endif
-
-#if CONFIG_SYS_I2C_BUS_MAX >= 3
-U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
-			 dw_i2c_write, dw_i2c_set_bus_speed,
-			 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
-#endif
-
-#if CONFIG_SYS_I2C_BUS_MAX >= 4
-U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
-			 dw_i2c_write, dw_i2c_set_bus_speed,
-			 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
-#endif
-
 #else /* CONFIG_DM_I2C */
 /* The DM I2C functions */
 
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 2200303ea8..eafd801cdc 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -538,24 +538,24 @@ static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
  */
 U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
-			 CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
+			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 			 0)
 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
 U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
-			 CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
+			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 			 1)
 #endif
 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
 U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
-			 CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
+			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 			 2)
 #endif
 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
 U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
-			 CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
+			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 			 3)
 #endif
 #else /* CONFIG_DM_I2C */
diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 85cf75ecd9..09f91e674d 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -190,11 +190,6 @@ __weak void i2c_init_board(void)
 {
 }
 
-/* implement possible for i2c specific early i2c init */
-__weak void i2c_early_init_f(void)
-{
-}
-
 /*
  * i2c_init_all():
  *
diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c
index 02f0144930..ecca90628e 100644
--- a/drivers/i2c/ihs_i2c.c
+++ b/drivers/i2c/ihs_i2c.c
@@ -6,19 +6,14 @@
 
 #include <common.h>
 #include <i2c.h>
-#if CONFIG_IS_ENABLED(DM_I2C)
 #include <dm.h>
 #include <regmap.h>
-#else
-#include <gdsys_fpga.h>
-#endif
 #include <log.h>
 #include <asm/global_data.h>
 #include <asm/unaligned.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
 
-#if CONFIG_IS_ENABLED(DM_I2C)
 struct ihs_i2c_priv {
 	uint speed;
 	struct regmap *map;
@@ -39,37 +34,6 @@ struct ihs_i2c_regs {
 #define ihs_i2c_get(map, member, valp) \
 	regmap_get(map, struct ihs_i2c_regs, member, valp)
 
-#else /* !CONFIG_DM_I2C */
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SYS_I2C_IHS_DUAL
-
-#define I2C_SET_REG(fld, val) \
-	do { \
-		if (I2C_ADAP_HWNR & 0x10) \
-			FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
-		else \
-			FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
-	} while (0)
-#else
-#define I2C_SET_REG(fld, val) \
-		FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
-#endif
-
-#ifdef CONFIG_SYS_I2C_IHS_DUAL
-#define I2C_GET_REG(fld, val) \
-	do {					\
-		if (I2C_ADAP_HWNR & 0x10) \
-			FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
-		else \
-			FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
-	} while (0)
-#else
-#define I2C_GET_REG(fld, val) \
-		FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
-#endif
-#endif /* CONFIG_DM_I2C */
-
 enum {
 	I2CINT_ERROR_EV = BIT(13),
 	I2CINT_TRANSMIT_EV = BIT(14),
@@ -91,23 +55,13 @@ enum {
 	I2COP_READ = 1,
 };
 
-#if CONFIG_IS_ENABLED(DM_I2C)
 static int wait_for_int(struct udevice *dev, int read)
-#else
-static int wait_for_int(bool read)
-#endif
 {
 	u16 val;
 	uint ctr = 0;
-#if CONFIG_IS_ENABLED(DM_I2C)
 	struct ihs_i2c_priv *priv = dev_get_priv(dev);
-#endif
 
-#if CONFIG_IS_ENABLED(DM_I2C)
 	ihs_i2c_get(priv->map, interrupt_status, &val);
-#else
-	I2C_GET_REG(interrupt_status, &val);
-#endif
 	/* Wait until error or receive/transmit interrupt was raised */
 	while (!(val & (I2CINT_ERROR_EV
 	       | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
@@ -116,40 +70,24 @@ static int wait_for_int(bool read)
 			debug("%s: timed out\n", __func__);
 			return -ETIMEDOUT;
 		}
-#if CONFIG_IS_ENABLED(DM_I2C)
 		ihs_i2c_get(priv->map, interrupt_status, &val);
-#else
-		I2C_GET_REG(interrupt_status, &val);
-#endif
 	}
 
 	return (val & I2CINT_ERROR_EV) ? -EIO : 0;
 }
 
-#if CONFIG_IS_ENABLED(DM_I2C)
 static int ihs_i2c_transfer(struct udevice *dev, uchar chip,
 			    uchar *buffer, int len, int read, bool is_last)
-#else
-static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
-			    bool is_last)
-#endif
 {
 	u16 val;
 	u16 data;
 	int res;
-#if CONFIG_IS_ENABLED(DM_I2C)
 	struct ihs_i2c_priv *priv = dev_get_priv(dev);
-#endif
 
 	/* Clear interrupt status */
 	data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
-#if CONFIG_IS_ENABLED(DM_I2C)
 	ihs_i2c_set(priv->map, interrupt_status, data);
 	ihs_i2c_get(priv->map, interrupt_status, &val);
-#else
-	I2C_SET_REG(interrupt_status, data);
-	I2C_GET_REG(interrupt_status, &val);
-#endif
 
 	/* If we want to write and have data, write the bytes to the mailbox */
 	if (!read && len) {
@@ -157,11 +95,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
 
 		if (len > 1)
 			val |= buffer[1] << 8;
-#if CONFIG_IS_ENABLED(DM_I2C)
 		ihs_i2c_set(priv->map, write_mailbox_ext, val);
-#else
-		I2C_SET_REG(write_mailbox_ext, val);
-#endif
 	}
 
 	data = I2CMB_NATIVE
@@ -170,17 +104,9 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
 	       | ((len > 1) ? I2CMB_2BYTE : 0)
 	       | (is_last ? 0 : I2CMB_HOLD_BUS);
 
-#if CONFIG_IS_ENABLED(DM_I2C)
 	ihs_i2c_set(priv->map, write_mailbox, data);
-#else
-	I2C_SET_REG(write_mailbox, data);
-#endif
 
-#if CONFIG_IS_ENABLED(DM_I2C)
 	res = wait_for_int(dev, read);
-#else
-	res = wait_for_int(read);
-#endif
 	if (res) {
 		if (res == -ETIMEDOUT)
 			debug("%s: time out while waiting for event\n", __func__);
@@ -190,11 +116,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
 
 	/* If we want to read, get the bytes from the mailbox */
 	if (read) {
-#if CONFIG_IS_ENABLED(DM_I2C)
 		ihs_i2c_get(priv->map, read_mailbox_ext, &val);
-#else
-		I2C_GET_REG(read_mailbox_ext, &val);
-#endif
 		buffer[0] = val & 0xff;
 		if (len > 1)
 			buffer[1] = val >> 8;
@@ -203,12 +125,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
 	return 0;
 }
 
-#if CONFIG_IS_ENABLED(DM_I2C)
 static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read)
-#else
-static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
-			       int read)
-#endif
 {
 	int res;
 
@@ -216,13 +133,8 @@ static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
 		int transfer = min(len, 2);
 		bool is_last = len <= transfer;
 
-#if CONFIG_IS_ENABLED(DM_I2C)
 		res = ihs_i2c_transfer(dev, chip, data, transfer, read,
 				       hold_bus ? false : is_last);
-#else
-		res = ihs_i2c_transfer(chip, data, transfer, read,
-				       hold_bus ? false : is_last);
-#endif
 		if (res)
 			return res;
 
@@ -233,27 +145,14 @@ static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
 	return 0;
 }
 
-#if CONFIG_IS_ENABLED(DM_I2C)
 static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen,
 			   bool hold_bus)
-#else
-static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus)
-#endif
 {
-#if CONFIG_IS_ENABLED(DM_I2C)
 	return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE);
-#else
-	return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE);
-#endif
 }
 
-#if CONFIG_IS_ENABLED(DM_I2C)
 static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr,
 			  int alen, uchar *buffer, int len, int read)
-#else
-static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
-			  int alen, uchar *buffer, int len, int read)
-#endif
 {
 	int res;
 
@@ -261,23 +160,13 @@ static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
 	if (len <= 0)
 		return -EINVAL;
 
-#if CONFIG_IS_ENABLED(DM_I2C)
 	res = ihs_i2c_address(dev, chip, addr, alen, len);
-#else
-	res = ihs_i2c_address(chip, addr, alen, len);
-#endif
 	if (res)
 		return res;
 
-#if CONFIG_IS_ENABLED(DM_I2C)
 	return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
-#else
-	return ihs_i2c_send_buffer(chip, buffer, len, false, read);
-#endif
 }
 
-#if CONFIG_IS_ENABLED(DM_I2C)
-
 int ihs_i2c_probe(struct udevice *bus)
 {
 	struct ihs_i2c_priv *priv = dev_get_priv(bus);
@@ -358,120 +247,3 @@ U_BOOT_DRIVER(i2c_ihs) = {
 	.priv_auto	= sizeof(struct ihs_i2c_priv),
 	.ops = &ihs_i2c_ops,
 };
-
-#else /* CONFIG_DM_I2C */
-
-static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
-{
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
-	/*
-	 * Call board specific i2c bus reset routine before accessing the
-	 * environment, which might be in a chip on that bus. For details
-	 * about this problem see doc/I2C_Edge_Conditions.
-	 */
-	i2c_init_board();
-#endif
-}
-
-static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
-{
-	uchar buffer[2];
-	int res;
-
-	res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true);
-	if (res)
-		return res;
-
-	return 0;
-}
-
-static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
-			int alen, uchar *buffer, int len)
-{
-	u8 addr_bytes[4];
-
-	put_unaligned_le32(addr, addr_bytes);
-
-	return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
-			      I2COP_READ);
-}
-
-static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
-			 int alen, uchar *buffer, int len)
-{
-	u8 addr_bytes[4];
-
-	put_unaligned_le32(addr, addr_bytes);
-
-	return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
-			      I2COP_WRITE);
-}
-
-static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
-					  unsigned int speed)
-{
-	if (speed != adap->speed)
-		return -EINVAL;
-	return speed;
-}
-
-/*
- * Register IHS i2c adapters
- */
-#ifdef CONFIG_SYS_I2C_IHS_CH0
-U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
-			 ihs_i2c_read, ihs_i2c_write,
-			 ihs_i2c_set_bus_speed,
-			 CONFIG_SYS_I2C_IHS_SPEED_0,
-			 CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
-#ifdef CONFIG_SYS_I2C_IHS_DUAL
-U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
-			 ihs_i2c_read, ihs_i2c_write,
-			 ihs_i2c_set_bus_speed,
-			 CONFIG_SYS_I2C_IHS_SPEED_0_1,
-			 CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
-#endif
-#endif
-#ifdef CONFIG_SYS_I2C_IHS_CH1
-U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
-			 ihs_i2c_read, ihs_i2c_write,
-			 ihs_i2c_set_bus_speed,
-			 CONFIG_SYS_I2C_IHS_SPEED_1,
-			 CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
-#ifdef CONFIG_SYS_I2C_IHS_DUAL
-U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
-			 ihs_i2c_read, ihs_i2c_write,
-			 ihs_i2c_set_bus_speed,
-			 CONFIG_SYS_I2C_IHS_SPEED_1_1,
-			 CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
-#endif
-#endif
-#ifdef CONFIG_SYS_I2C_IHS_CH2
-U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
-			 ihs_i2c_read, ihs_i2c_write,
-			 ihs_i2c_set_bus_speed,
-			 CONFIG_SYS_I2C_IHS_SPEED_2,
-			 CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
-#ifdef CONFIG_SYS_I2C_IHS_DUAL
-U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
-			 ihs_i2c_read, ihs_i2c_write,
-			 ihs_i2c_set_bus_speed,
-			 CONFIG_SYS_I2C_IHS_SPEED_2_1,
-			 CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
-#endif
-#endif
-#ifdef CONFIG_SYS_I2C_IHS_CH3
-U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
-			 ihs_i2c_read, ihs_i2c_write,
-			 ihs_i2c_set_bus_speed,
-			 CONFIG_SYS_I2C_IHS_SPEED_3,
-			 CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
-#ifdef CONFIG_SYS_I2C_IHS_DUAL
-U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
-			 ihs_i2c_read, ihs_i2c_write,
-			 ihs_i2c_set_bus_speed,
-			 CONFIG_SYS_I2C_IHS_SPEED_3_1,
-			 CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
-#endif
-#endif
-#endif /* CONFIG_DM_I2C */
diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
index 20c5de0007..0eff353161 100644
--- a/drivers/i2c/mv_i2c.c
+++ b/drivers/i2c/mv_i2c.c
@@ -80,7 +80,7 @@ static void i2c_reset(struct mv_i2c *base)
 
 	i2c_clk_enable();
 
-	writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */
+	writel(0x0, &base->isar); /* set our slave address */
 	/* set control reg values */
 	writel(I2C_ICR_INIT | icr_mode, &base->icr);
 	writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 003aa33f6e..5057bd9665 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -110,32 +110,6 @@ static u16 i2c_clk_div[50][2] = {
 };
 #endif
 
-#ifndef CONFIG_SYS_MXC_I2C1_SPEED
-#define CONFIG_SYS_MXC_I2C1_SPEED 100000
-#endif
-#ifndef CONFIG_SYS_MXC_I2C2_SPEED
-#define CONFIG_SYS_MXC_I2C2_SPEED 100000
-#endif
-#ifndef CONFIG_SYS_MXC_I2C3_SPEED
-#define CONFIG_SYS_MXC_I2C3_SPEED 100000
-#endif
-#ifndef CONFIG_SYS_MXC_I2C4_SPEED
-#define CONFIG_SYS_MXC_I2C4_SPEED 100000
-#endif
-
-#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
-#define CONFIG_SYS_MXC_I2C1_SLAVE 0
-#endif
-#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
-#define CONFIG_SYS_MXC_I2C2_SLAVE 0
-#endif
-#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
-#define CONFIG_SYS_MXC_I2C3_SLAVE 0
-#endif
-#ifndef CONFIG_SYS_MXC_I2C4_SLAVE
-#define CONFIG_SYS_MXC_I2C4_SLAVE 0
-#endif
-
 /*
  * Calculate and set proper clock divider
  */
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 71f6f5f7ac..e2c8c005d9 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -936,62 +936,34 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
 	return __omap24_i2c_probe(i2c_base, ip_rev, adap->waitdelay, chip);
 }
 
-#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
-#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
-#endif
-#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
-#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
-#endif
-
 U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
 			 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
-			 CONFIG_SYS_OMAP24_I2C_SPEED,
-			 CONFIG_SYS_OMAP24_I2C_SLAVE,
+			 CONFIG_SYS_I2C_SPEED,
+			 CONFIG_SYS_I2C_SLAVE,
 			 0)
 U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
 			 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
-			 CONFIG_SYS_OMAP24_I2C_SPEED1,
-			 CONFIG_SYS_OMAP24_I2C_SLAVE1,
+			 CONFIG_SYS_I2C_SPEED,
+			 CONFIG_SYS_I2C_SLAVE,
 			 1)
 
 #if (CONFIG_SYS_I2C_BUS_MAX > 2)
-#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
-#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
-#endif
-#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
-#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
-#endif
-
 U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
 			 omap24_i2c_read, omap24_i2c_write, NULL,
-			 CONFIG_SYS_OMAP24_I2C_SPEED2,
-			 CONFIG_SYS_OMAP24_I2C_SLAVE2,
+			 CONFIG_SYS_I2C_SPEED,
+			 CONFIG_SYS_I2C_SLAVE,
 			 2)
 #if (CONFIG_SYS_I2C_BUS_MAX > 3)
-#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
-#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
-#endif
-#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
-#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
-#endif
-
 U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
 			 omap24_i2c_read, omap24_i2c_write, NULL,
-			 CONFIG_SYS_OMAP24_I2C_SPEED3,
-			 CONFIG_SYS_OMAP24_I2C_SLAVE3,
+			 CONFIG_SYS_I2C_SPEED,
+			 CONFIG_SYS_I2C_SLAVE,
 			 3)
 #if (CONFIG_SYS_I2C_BUS_MAX > 4)
-#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
-#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
-#endif
-#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
-#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
-#endif
-
 U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
 			 omap24_i2c_read, omap24_i2c_write, NULL,
-			 CONFIG_SYS_OMAP24_I2C_SPEED4,
-			 CONFIG_SYS_OMAP24_I2C_SLAVE4,
+			 CONFIG_SYS_I2C_SPEED,
+			 CONFIG_SYS_I2C_SLAVE,
 			 4)
 #endif
 #endif
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index 56f0f69885..e0f499d759 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -21,12 +21,6 @@
 #include <i2c.h>
 #include "s3c24x0_i2c.h"
 
-#ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE
-#define SYS_I2C_S3C24X0_SLAVE_ADDR	0
-#else
-#define SYS_I2C_S3C24X0_SLAVE_ADDR	CONFIG_SYS_I2C_S3C24X0_SLAVE
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -83,6 +77,8 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
 	writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 }
 
+#define SYS_I2C_S3C24X0_SLAVE_ADDR	0
+
 static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 {
 	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index 26a8700669..6cecec4145 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -294,20 +294,20 @@ static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
  * Register RCAR i2c adapters
  */
 U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
-	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
+	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 0)
 #ifdef CONFIG_SYS_I2C_SH_BASE1
 U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
-	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
+	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 1)
 #endif
 #ifdef CONFIG_SYS_I2C_SH_BASE2
 U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
-	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
+	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 2)
 #endif
 #ifdef CONFIG_SYS_I2C_SH_BASE3
 U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
-	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
+	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 3)
 #endif
 #ifdef CONFIG_SYS_I2C_SH_BASE4
 U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
-	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
+	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 4)
 #endif
diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c
index db69c18cb6..c72839eb01 100644
--- a/drivers/i2c/soft_i2c.c
+++ b/drivers/i2c/soft_i2c.c
@@ -438,80 +438,3 @@ U_BOOT_I2C_ADAP_COMPLETE(soft00, soft_i2c_init, soft_i2c_probe,
 			 soft_i2c_read, soft_i2c_write, NULL,
 			 CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE,
 			 0)
-#if defined(I2C_SOFT_DECLARATIONS2)
-U_BOOT_I2C_ADAP_COMPLETE(soft01, soft_i2c_init, soft_i2c_probe,
-			 soft_i2c_read, soft_i2c_write, NULL,
-			 CONFIG_SYS_I2C_SOFT_SPEED_2,
-			 CONFIG_SYS_I2C_SOFT_SLAVE_2,
-			 1)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS3)
-U_BOOT_I2C_ADAP_COMPLETE(soft02, soft_i2c_init, soft_i2c_probe,
-			 soft_i2c_read, soft_i2c_write, NULL,
-			 CONFIG_SYS_I2C_SOFT_SPEED_3,
-			 CONFIG_SYS_I2C_SOFT_SLAVE_3,
-			 2)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS4)
-U_BOOT_I2C_ADAP_COMPLETE(soft03, soft_i2c_init, soft_i2c_probe,
-			 soft_i2c_read, soft_i2c_write, NULL,
-			 CONFIG_SYS_I2C_SOFT_SPEED_4,
-			 CONFIG_SYS_I2C_SOFT_SLAVE_4,
-			 3)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS5)
-U_BOOT_I2C_ADAP_COMPLETE(soft04, soft_i2c_init, soft_i2c_probe,
-			 soft_i2c_read, soft_i2c_write, NULL,
-			 CONFIG_SYS_I2C_SOFT_SPEED_5,
-			 CONFIG_SYS_I2C_SOFT_SLAVE_5,
-			 4)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS6)
-U_BOOT_I2C_ADAP_COMPLETE(soft05, soft_i2c_init, soft_i2c_probe,
-			 soft_i2c_read, soft_i2c_write, NULL,
-			 CONFIG_SYS_I2C_SOFT_SPEED_6,
-			 CONFIG_SYS_I2C_SOFT_SLAVE_6,
-			 5)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS7)
-U_BOOT_I2C_ADAP_COMPLETE(soft06, soft_i2c_init, soft_i2c_probe,
-			 soft_i2c_read, soft_i2c_write, NULL,
-			 CONFIG_SYS_I2C_SOFT_SPEED_7,
-			 CONFIG_SYS_I2C_SOFT_SLAVE_7,
-			 6)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS8)
-U_BOOT_I2C_ADAP_COMPLETE(soft07, soft_i2c_init, soft_i2c_probe,
-			 soft_i2c_read, soft_i2c_write, NULL,
-			 CONFIG_SYS_I2C_SOFT_SPEED_8,
-			 CONFIG_SYS_I2C_SOFT_SLAVE_8,
-			 7)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS9)
-U_BOOT_I2C_ADAP_COMPLETE(soft08, soft_i2c_init, soft_i2c_probe,
-			 soft_i2c_read, soft_i2c_write, NULL,
-			 CONFIG_SYS_I2C_SOFT_SPEED_9,
-			 CONFIG_SYS_I2C_SOFT_SLAVE_9,
-			 8)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS10)
-U_BOOT_I2C_ADAP_COMPLETE(soft09, soft_i2c_init, soft_i2c_probe,
-			 soft_i2c_read, soft_i2c_write, NULL,
-			 CONFIG_SYS_I2C_SOFT_SPEED_10,
-			 CONFIG_SYS_I2C_SOFT_SLAVE_10,
-			 9)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS11)
-U_BOOT_I2C_ADAP_COMPLETE(soft10, soft_i2c_init, soft_i2c_probe,
-			 soft_i2c_read, soft_i2c_write, NULL,
-			 CONFIG_SYS_I2C_SOFT_SPEED_11,
-			 CONFIG_SYS_I2C_SOFT_SLAVE_11,
-			 10)
-#endif
-#if defined(I2C_SOFT_DECLARATIONS12)
-U_BOOT_I2C_ADAP_COMPLETE(soft11, soft_i2c_init, soft_i2c_probe,
-			 soft_i2c_read, soft_i2c_write, NULL,
-			 CONFIG_SYS_I2C_SOFT_SPEED_12,
-			 CONFIG_SYS_I2C_SOFT_SLAVE_12,
-			 11)
-#endif
diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c
index 565d99e7e5..d3743dc37f 100644
--- a/drivers/input/i8042.c
+++ b/drivers/input/i8042.c
@@ -150,8 +150,8 @@ static int kbd_reset(int quirk)
 	else if ((quirk & QUIRK_DUP_POR) && config == KBD_POR)
 		config = kbd_cmd_read(CMD_RD_CONFIG);
 
-	config |= CONFIG_AT_TRANS;
-	config &= ~(CONFIG_KIRQ_EN | CONFIG_MIRQ_EN);
+	config |= CFG_AT_TRANS;
+	config &= ~(CFG_KIRQ_EN | CFG_MIRQ_EN);
 	if (kbd_cmd_write(CMD_WR_CONFIG, config))
 		goto err;
 
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 997b713221..099ff29348 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -398,36 +398,12 @@ config SPL_I2C_EEPROM
 	  This option is an SPL-variant of the I2C_EEPROM option.
 	  See the help of I2C_EEPROM for details.
 
-if I2C_EEPROM
-
 config SYS_I2C_EEPROM_ADDR
 	hex "Chip address of the EEPROM device"
+	depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
 	default 0
 
-config SYS_I2C_EEPROM_BUS
-	int "I2C bus of the EEPROM device."
-	default 0
-
-config SYS_EEPROM_SIZE
-	int "Size in bytes of the EEPROM device"
-	default 256
-
-config SYS_EEPROM_PAGE_WRITE_BITS
-	int "Number of bits used to address bytes in a single page"
-	default 0
-	help
-	  The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
-	  A 64 byte page, for example would require six bits.
-
-config SYS_EEPROM_PAGE_WRITE_DELAY_MS
-	int "Number of milliseconds to delay between page writes"
-	default 0
-
-config SYS_I2C_EEPROM_ADDR_LEN
-	int "Length in bytes of the EEPROM memory array address"
-	default 1
-	help
-	  Note: This is NOT the chip address length!
+if I2C_EEPROM
 
 config SYS_I2C_EEPROM_ADDR_OVERFLOW
 	hex "EEPROM Address Overflow"
diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c
index e33953ec7c..13fd631cb4 100644
--- a/drivers/mtd/nand/raw/vf610_nfc.c
+++ b/drivers/mtd/nand/raw/vf610_nfc.c
@@ -109,19 +109,19 @@
 #define STATUS_BYTE1_MASK			0x000000FF
 
 /* NFC_FLASH_CONFIG Field */
-#define CONFIG_ECC_SRAM_ADDR_MASK		0x7FC00000
-#define CONFIG_ECC_SRAM_ADDR_SHIFT		22
-#define CONFIG_ECC_SRAM_REQ_BIT			(1<<21)
-#define CONFIG_DMA_REQ_BIT			(1<<20)
-#define CONFIG_ECC_MODE_MASK			0x000E0000
-#define CONFIG_ECC_MODE_SHIFT			17
-#define CONFIG_FAST_FLASH_BIT			(1<<16)
-#define CONFIG_16BIT				(1<<7)
-#define CONFIG_BOOT_MODE_BIT			(1<<6)
-#define CONFIG_ADDR_AUTO_INCR_BIT		(1<<5)
-#define CONFIG_BUFNO_AUTO_INCR_BIT		(1<<4)
-#define CONFIG_PAGE_CNT_MASK			0xF
-#define CONFIG_PAGE_CNT_SHIFT			0
+#define CFG_ECC_SRAM_ADDR_MASK			0x7FC00000
+#define CFG_ECC_SRAM_ADDR_SHIFT			22
+#define CFG_ECC_SRAM_REQ_BIT			(1<<21)
+#define CFG_DMA_REQ_BIT				(1<<20)
+#define CFG_ECC_MODE_MASK			0x000E0000
+#define CFG_ECC_MODE_SHIFT			17
+#define CFG_FAST_FLASH_BIT			(1<<16)
+#define CFG_16BIT				(1<<7)
+#define CFG_BOOT_MODE_BIT			(1<<6)
+#define CFG_ADDR_AUTO_INCR_BIT			(1<<5)
+#define CFG_BUFNO_AUTO_INCR_BIT			(1<<4)
+#define CFG_PAGE_CNT_MASK			0xF
+#define CFG_PAGE_CNT_SHIFT			0
 
 /* NFC_IRQ_STATUS Field */
 #define IDLE_IRQ_BIT				(1<<29)
@@ -342,8 +342,8 @@ static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
 static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode)
 {
 	vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
-			    CONFIG_ECC_MODE_MASK,
-			    CONFIG_ECC_MODE_SHIFT, ecc_mode);
+			    CFG_ECC_MODE_MASK,
+			    CFG_ECC_MODE_SHIFT, ecc_mode);
 }
 
 static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size)
@@ -666,16 +666,16 @@ static int vf610_nfc_nand_init(struct vf610_nfc *nfc, int devnum)
 	chip->ecc.size = PAGE_2K;
 
 	/* Set configuration register. */
-	vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
-	vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
-	vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
-	vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
-	vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
-	vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
+	vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_16BIT);
+	vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_ADDR_AUTO_INCR_BIT);
+	vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_BUFNO_AUTO_INCR_BIT);
+	vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_BOOT_MODE_BIT);
+	vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_DMA_REQ_BIT);
+	vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_FAST_FLASH_BIT);
 
 	/* Disable virtual pages, only one elementary transfer unit */
-	vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
-			    CONFIG_PAGE_CNT_SHIFT, 1);
+	vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CFG_PAGE_CNT_MASK,
+			    CFG_PAGE_CNT_SHIFT, 1);
 
 	/* first scan to find the device and get the page size */
 	if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
@@ -684,7 +684,7 @@ static int vf610_nfc_nand_init(struct vf610_nfc *nfc, int devnum)
 	}
 
 	if (cfg.width == 16)
-		vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
+		vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_16BIT);
 
 	/* Bad block options. */
 	if (cfg.flash_bbt)
@@ -734,12 +734,12 @@ static int vf610_nfc_nand_init(struct vf610_nfc *nfc, int devnum)
 
 		/* Set ECC_STATUS offset */
 		vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
-				    CONFIG_ECC_SRAM_ADDR_MASK,
-				    CONFIG_ECC_SRAM_ADDR_SHIFT,
+				    CFG_ECC_SRAM_ADDR_MASK,
+				    CFG_ECC_SRAM_ADDR_SHIFT,
 				    ECC_SRAM_ADDR >> 3);
 
 		/* Enable ECC status in SRAM */
-		vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
+		vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_ECC_SRAM_REQ_BIT);
 	}
 
 	/* second phase scan */
diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h
index 4c3acba35a..db324c17d6 100644
--- a/drivers/net/smc91111.h
+++ b/drivers/net/smc91111.h
@@ -251,18 +251,14 @@ struct smc91111_priv{
  * We have only 16 Bit PCMCIA access on Socket 0
  */
 
-#ifdef CONFIG_ADNPESC1
-#define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+((r)<<1))))
-#elif CONFIG_ARM64
+#if CONFIG_ARM64
 #define	SMC_inw(a, r)	(*((volatile word*)((a)->iobase+((dword)(r)))))
 #else
 #define SMC_inw(a, r)	(*((volatile word*)((a)->iobase+(r))))
 #endif
 #define  SMC_inb(a,r)	(((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF))
 
-#ifdef CONFIG_ADNPESC1
-#define	SMC_outw(a,d,r)	(*((volatile word *)((a)->iobase+((r)<<1))) = d)
-#elif CONFIG_ARM64
+#if CONFIG_ARM64
 #define	SMC_outw(a, d, r)	\
 			(*((volatile word*)((a)->iobase+((dword)(r)))) = d)
 #else
@@ -442,11 +438,6 @@ struct smc91111_priv{
 #define RPC_DEFAULT	( RPC_SPEED | RPC_DPLX | RPC_ANEG	\
 			| (RPC_LED_TX_RX << RPC_LSXA_SHFT)	\
 			| (RPC_LED_100_10 << RPC_LSXB_SHFT)	)
-#elif defined(CONFIG_ADNPESC1)
-/* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */
-#define RPC_DEFAULT	( RPC_SPEED | RPC_DPLX | RPC_ANEG	\
-			| (RPC_LED_TX_RX << RPC_LSXA_SHFT)	\
-			| (RPC_LED_100_10 << RPC_LSXB_SHFT)	)
 #else
 /* SMSC reference design: LEDa --> green, LEDb --> yellow */
 #define RPC_DEFAULT	( RPC_SPEED | RPC_DPLX | RPC_ANEG	\
diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c
index fadc9f3965..989679e881 100644
--- a/drivers/spi/altera_spi.c
+++ b/drivers/spi/altera_spi.c
@@ -19,9 +19,7 @@
 #define ALTERA_SPI_STATUS_RRDY_MSK	BIT(7)
 #define ALTERA_SPI_CONTROL_SSO_MSK	BIT(10)
 
-#ifndef CONFIG_ALTERA_SPI_IDLE_VAL
-#define CONFIG_ALTERA_SPI_IDLE_VAL	0xff
-#endif
+#define ALTERA_SPI_IDLE_VAL		0xff
 
 struct altera_spi_regs {
 	u32	rxdata;
@@ -119,7 +117,7 @@ static int altera_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		if (txp)
 			data = *txp++;
 		else
-			data = CONFIG_ALTERA_SPI_IDLE_VAL;
+			data = ALTERA_SPI_IDLE_VAL;
 
 		debug("%s: tx:%x ", __func__, data);
 		writel(data, &regs->txdata);
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 43cc2e0433..23060fc369 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -86,14 +86,14 @@ static void init_fslspclksel(struct dwc2_core_regs *regs)
 {
 	uint32_t phyclk;
 
-#if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
+#if (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
 	phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;	/* Full speed PHY */
 #else
 	/* High speed PHY running at full speed or high speed */
 	phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
 #endif
 
-#ifdef CONFIG_DWC2_ULPI_FS_LS
+#ifdef DWC2_ULPI_FS_LS
 	uint32_t hwcfg2 = readl(&regs->ghwcfg2);
 	uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
 			DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
@@ -257,28 +257,28 @@ static void dwc_otg_core_host_init(struct udevice *dev,
 
 	/* Initialize Host Configuration Register */
 	init_fslspclksel(regs);
-#ifdef CONFIG_DWC2_DFLT_SPEED_FULL
+#ifdef DWC2_DFLT_SPEED_FULL
 	setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
 #endif
 
 	/* Configure data FIFO sizes */
-#ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
+#ifdef DWC2_ENABLE_DYNAMIC_FIFO
 	if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
 		/* Rx FIFO */
-		writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
+		writel(DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
 
 		/* Non-periodic Tx FIFO */
-		nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
+		nptxfifosize |= DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
 				DWC2_FIFOSIZE_DEPTH_OFFSET;
-		nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
+		nptxfifosize |= DWC2_HOST_RX_FIFO_SIZE <<
 				DWC2_FIFOSIZE_STARTADDR_OFFSET;
 		writel(nptxfifosize, &regs->gnptxfsiz);
 
 		/* Periodic Tx FIFO */
-		ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
+		ptxfifosize |= DWC2_HOST_PERIO_TX_FIFO_SIZE <<
 				DWC2_FIFOSIZE_DEPTH_OFFSET;
-		ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
-				CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
+		ptxfifosize |= (DWC2_HOST_RX_FIFO_SIZE +
+				DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
 				DWC2_FIFOSIZE_STARTADDR_OFFSET;
 		writel(ptxfifosize, &regs->hptxfsiz);
 	}
@@ -340,7 +340,7 @@ static void dwc_otg_core_init(struct udevice *dev)
 	struct dwc2_core_regs *regs = priv->regs;
 	uint32_t ahbcfg = 0;
 	uint32_t usbcfg = 0;
-	uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
+	uint8_t brst_sz = DWC2_DMA_BURST_SIZE;
 
 	/* Common Initialization */
 	usbcfg = readl(&regs->gusbcfg);
@@ -357,7 +357,7 @@ static void dwc_otg_core_init(struct udevice *dev)
 	}
 
 	/* Set external TS Dline pulsing */
-#ifdef CONFIG_DWC2_TS_DLINE
+#ifdef DWC2_TS_DLINE
 	usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 #else
 	usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
@@ -371,8 +371,8 @@ static void dwc_otg_core_init(struct udevice *dev)
 	 * This programming sequence needs to happen in FS mode before
 	 * any other programming occurs
 	 */
-#if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
-	(CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
+#if defined(DWC2_DFLT_SPEED_FULL) && \
+	(DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
 	/* If FS mode with FS PHY */
 	setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
 
@@ -387,7 +387,7 @@ static void dwc_otg_core_init(struct udevice *dev)
 	if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
 		init_fslspclksel(regs);
 
-#ifdef CONFIG_DWC2_I2C_ENABLE
+#ifdef DWC2_I2C_ENABLE
 	/* Program GUSBCFG.OtgUtmifsSel to I2C */
 	setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
 
@@ -407,16 +407,16 @@ static void dwc_otg_core_init(struct udevice *dev)
 	 * immediately after setting phyif.
 	 */
 	usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
-	usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
+	usbcfg |= DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
 
 	if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) {	/* ULPI interface */
-#ifdef CONFIG_DWC2_PHY_ULPI_DDR
+#ifdef DWC2_PHY_ULPI_DDR
 		usbcfg |= DWC2_GUSBCFG_DDRSEL;
 #else
 		usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
 #endif
 	} else {	/* UTMI+ interface */
-#if (CONFIG_DWC2_UTMI_WIDTH == 16)
+#if (DWC2_UTMI_WIDTH == 16)
 		usbcfg |= DWC2_GUSBCFG_PHYIF;
 #endif
 	}
@@ -429,7 +429,7 @@ static void dwc_otg_core_init(struct udevice *dev)
 
 	usbcfg = readl(&regs->gusbcfg);
 	usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
-#ifdef CONFIG_DWC2_ULPI_FS_LS
+#ifdef DWC2_ULPI_FS_LS
 	uint32_t hwcfg2 = readl(&regs->ghwcfg2);
 	uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
 			DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
@@ -456,14 +456,14 @@ static void dwc_otg_core_init(struct udevice *dev)
 			brst_sz >>= 1;
 		}
 
-#ifdef CONFIG_DWC2_DMA_ENABLE
+#ifdef DWC2_DMA_ENABLE
 		ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 #endif
 		break;
 
 	case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
 		ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
-#ifdef CONFIG_DWC2_DMA_ENABLE
+#ifdef DWC2_DMA_ENABLE
 		ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 #endif
 		break;
@@ -476,7 +476,7 @@ static void dwc_otg_core_init(struct udevice *dev)
 
 	if (!priv->hnp_srp_disable)
 		usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
-#ifdef CONFIG_DWC2_IC_USB_CAP
+#ifdef DWC2_IC_USB_CAP
 	usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
 #endif
 
@@ -939,9 +939,9 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 	debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
 	      in, len);
 
-	max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
-	if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
-		max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
+	max_xfer_len = DWC2_MAX_PACKET_COUNT * max;
+	if (max_xfer_len > DWC2_MAX_TRANSFER_SIZE)
+		max_xfer_len = DWC2_MAX_TRANSFER_SIZE;
 	if (max_xfer_len > DWC2_DATA_BUF_SIZE)
 		max_xfer_len = DWC2_DATA_BUF_SIZE;
 
@@ -1198,7 +1198,7 @@ static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
 		return -ENODEV;
 	}
 
-#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
+#ifdef DWC2_PHY_ULPI_EXT_VBUS
 	priv->ext_vbus = 1;
 #else
 	priv->ext_vbus = 0;
diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h
index 97a06c48f2..a6f562fe60 100644
--- a/drivers/usb/host/dwc2.h
+++ b/drivers/usb/host/dwc2.h
@@ -759,32 +759,32 @@ struct dwc2_core_regs {
 #define RH_B_PPCM	0xffff0000	/* port power control mask */
 
 /* Default driver configuration */
-#define CONFIG_DWC2_DMA_ENABLE
-#define CONFIG_DWC2_DMA_BURST_SIZE		32	/* DMA burst len */
-#undef CONFIG_DWC2_DFLT_SPEED_FULL		/* Do not force DWC2 to FS */
-#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO		/* Runtime FIFO size detect */
-#define CONFIG_DWC2_MAX_CHANNELS		16	/* Max # of EPs */
-#define CONFIG_DWC2_HOST_RX_FIFO_SIZE		(516 + CONFIG_DWC2_MAX_CHANNELS)
-#define CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE	0x100	/* nPeriodic TX FIFO */
-#define CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE	0x200	/* Periodic TX FIFO */
-#define CONFIG_DWC2_MAX_TRANSFER_SIZE		65535
-#define CONFIG_DWC2_MAX_PACKET_COUNT		511
+#define DWC2_DMA_ENABLE
+#define DWC2_DMA_BURST_SIZE		32	/* DMA burst len */
+#undef DWC2_DFLT_SPEED_FULL		/* Do not force DWC2 to FS */
+#define DWC2_ENABLE_DYNAMIC_FIFO		/* Runtime FIFO size detect */
+#define DWC2_MAX_CHANNELS		16	/* Max # of EPs */
+#define DWC2_HOST_RX_FIFO_SIZE		(516 + DWC2_MAX_CHANNELS)
+#define DWC2_HOST_NPERIO_TX_FIFO_SIZE	0x100	/* nPeriodic TX FIFO */
+#define DWC2_HOST_PERIO_TX_FIFO_SIZE	0x200	/* Periodic TX FIFO */
+#define DWC2_MAX_TRANSFER_SIZE		65535
+#define DWC2_MAX_PACKET_COUNT		511
 
 #define DWC2_PHY_TYPE_FS		0
 #define DWC2_PHY_TYPE_UTMI		1
 #define DWC2_PHY_TYPE_ULPI		2
-#define CONFIG_DWC2_PHY_TYPE		DWC2_PHY_TYPE_UTMI	/* PHY type */
-#ifndef CONFIG_DWC2_UTMI_WIDTH
-#define CONFIG_DWC2_UTMI_WIDTH		8	/* UTMI bus width (8/16) */
+#define DWC2_PHY_TYPE		DWC2_PHY_TYPE_UTMI	/* PHY type */
+#ifndef DWC2_UTMI_WIDTH
+#define DWC2_UTMI_WIDTH		8	/* UTMI bus width (8/16) */
 #endif
 
-#undef CONFIG_DWC2_PHY_ULPI_DDR			/* ULPI PHY uses DDR mode */
-#define CONFIG_DWC2_PHY_ULPI_EXT_VBUS		/* ULPI PHY controls VBUS */
-#undef CONFIG_DWC2_I2C_ENABLE			/* Enable I2C */
-#undef CONFIG_DWC2_ULPI_FS_LS			/* ULPI is FS/LS */
-#undef CONFIG_DWC2_TS_DLINE			/* External DLine pulsing */
-#undef CONFIG_DWC2_THR_CTL			/* Threshold control */
-#define CONFIG_DWC2_TX_THR_LENGTH		64
-#undef CONFIG_DWC2_IC_USB_CAP			/* IC Cap */
+#undef DWC2_PHY_ULPI_DDR			/* ULPI PHY uses DDR mode */
+#define DWC2_PHY_ULPI_EXT_VBUS		/* ULPI PHY controls VBUS */
+#undef DWC2_I2C_ENABLE			/* Enable I2C */
+#undef DWC2_ULPI_FS_LS			/* ULPI is FS/LS */
+#undef DWC2_TS_DLINE			/* External DLine pulsing */
+#undef DWC2_THR_CTL			/* Threshold control */
+#define DWC2_TX_THR_LENGTH		64
+#undef DWC2_IC_USB_CAP			/* IC Cap */
 
 #endif	/* __DWC2_H__ */
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 7ae0ab2b35..f6d07b343f 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -25,7 +25,6 @@ obj-${CONFIG_VIDEO_STM32} += stm32/
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
 obj-y += ti/
 
-obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
 obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
 obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
 obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o
diff --git a/drivers/video/ati_ids.h b/drivers/video/ati_ids.h
deleted file mode 100644
index 3e72a7dd4c..0000000000
--- a/drivers/video/ati_ids.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * ATI PCI IDs from XFree86, kept here to make sync'ing with
- * XFree much simpler. Currently, this list is only used by
- * radeonfb
- */
-
-#define PCI_CHIP_RV380_3150             0x3150
-#define PCI_CHIP_RV380_3151             0x3151
-#define PCI_CHIP_RV380_3152             0x3152
-#define PCI_CHIP_RV380_3153             0x3153
-#define PCI_CHIP_RV380_3154             0x3154
-#define PCI_CHIP_RV380_3156             0x3156
-#define PCI_CHIP_RV380_3E50             0x3E50
-#define PCI_CHIP_RV380_3E51             0x3E51
-#define PCI_CHIP_RV380_3E52             0x3E52
-#define PCI_CHIP_RV380_3E53             0x3E53
-#define PCI_CHIP_RV380_3E54             0x3E54
-#define PCI_CHIP_RV380_3E56             0x3E56
-#define PCI_CHIP_RS100_4136		0x4136
-#define PCI_CHIP_RS200_4137		0x4137
-#define PCI_CHIP_R300_AD		0x4144
-#define PCI_CHIP_R300_AE		0x4145
-#define PCI_CHIP_R300_AF		0x4146
-#define PCI_CHIP_R300_AG		0x4147
-#define PCI_CHIP_R350_AH                0x4148
-#define PCI_CHIP_R350_AI                0x4149
-#define PCI_CHIP_R350_AJ                0x414A
-#define PCI_CHIP_R350_AK                0x414B
-#define PCI_CHIP_RV350_AP               0x4150
-#define PCI_CHIP_RV350_AQ               0x4151
-#define PCI_CHIP_RV360_AR               0x4152
-#define PCI_CHIP_RV350_AS               0x4153
-#define PCI_CHIP_RV350_AT               0x4154
-#define PCI_CHIP_RV350_AV               0x4156
-#define PCI_CHIP_MACH32		0x4158
-#define PCI_CHIP_RS250_4237		0x4237
-#define PCI_CHIP_R200_BB		0x4242
-#define PCI_CHIP_R200_BC		0x4243
-#define PCI_CHIP_RS100_4336		0x4336
-#define PCI_CHIP_RS200_4337		0x4337
-#define PCI_CHIP_MACH64CT		0x4354
-#define PCI_CHIP_MACH64CX		0x4358
-#define PCI_CHIP_RS250_4437		0x4437
-#define PCI_CHIP_MACH64ET		0x4554
-#define PCI_CHIP_MACH64GB		0x4742
-#define PCI_CHIP_MACH64GD		0x4744
-#define PCI_CHIP_MACH64GI		0x4749
-#define PCI_CHIP_MACH64GL		0x474C
-#define PCI_CHIP_MACH64GM		0x474D
-#define PCI_CHIP_MACH64GN		0x474E
-#define PCI_CHIP_MACH64GO		0x474F
-#define PCI_CHIP_MACH64GP		0x4750
-#define PCI_CHIP_MACH64GQ		0x4751
-#define PCI_CHIP_MACH64GR		0x4752
-#define PCI_CHIP_MACH64GS		0x4753
-#define PCI_CHIP_MACH64GT		0x4754
-#define PCI_CHIP_MACH64GU		0x4755
-#define PCI_CHIP_MACH64GV		0x4756
-#define PCI_CHIP_MACH64GW		0x4757
-#define PCI_CHIP_MACH64GX		0x4758
-#define PCI_CHIP_MACH64GY		0x4759
-#define PCI_CHIP_MACH64GZ		0x475A
-#define PCI_CHIP_RV250_Id		0x4964
-#define PCI_CHIP_RV250_Ie		0x4965
-#define PCI_CHIP_RV250_If		0x4966
-#define PCI_CHIP_RV250_Ig		0x4967
-#define PCI_CHIP_R420_JH                0x4A48
-#define PCI_CHIP_R420_JI                0x4A49
-#define PCI_CHIP_R420_JJ                0x4A4A
-#define PCI_CHIP_R420_JK                0x4A4B
-#define PCI_CHIP_R420_JL                0x4A4C
-#define PCI_CHIP_R420_JM                0x4A4D
-#define PCI_CHIP_R420_JN                0x4A4E
-#define PCI_CHIP_R420_JP                0x4A50
-#define PCI_CHIP_MACH64LB		0x4C42
-#define PCI_CHIP_MACH64LD		0x4C44
-#define PCI_CHIP_RAGE128LE		0x4C45
-#define PCI_CHIP_RAGE128LF		0x4C46
-#define PCI_CHIP_MACH64LG		0x4C47
-#define PCI_CHIP_MACH64LI		0x4C49
-#define PCI_CHIP_MACH64LM		0x4C4D
-#define PCI_CHIP_MACH64LN		0x4C4E
-#define PCI_CHIP_MACH64LP		0x4C50
-#define PCI_CHIP_MACH64LQ		0x4C51
-#define PCI_CHIP_MACH64LR		0x4C52
-#define PCI_CHIP_MACH64LS		0x4C53
-#define PCI_CHIP_MACH64LT		0x4C54
-#define PCI_CHIP_RADEON_LW		0x4C57
-#define PCI_CHIP_RADEON_LX		0x4C58
-#define PCI_CHIP_RADEON_LY		0x4C59
-#define PCI_CHIP_RADEON_LZ		0x4C5A
-#define PCI_CHIP_RV250_Ld		0x4C64
-#define PCI_CHIP_RV250_Le		0x4C65
-#define PCI_CHIP_RV250_Lf		0x4C66
-#define PCI_CHIP_RV250_Lg		0x4C67
-#define PCI_CHIP_RV250_Ln		0x4C6E
-#define PCI_CHIP_RAGE128MF		0x4D46
-#define PCI_CHIP_RAGE128ML		0x4D4C
-#define PCI_CHIP_R300_ND		0x4E44
-#define PCI_CHIP_R300_NE		0x4E45
-#define PCI_CHIP_R300_NF		0x4E46
-#define PCI_CHIP_R300_NG		0x4E47
-#define PCI_CHIP_R350_NH                0x4E48
-#define PCI_CHIP_R350_NI                0x4E49
-#define PCI_CHIP_R360_NJ                0x4E4A
-#define PCI_CHIP_R350_NK                0x4E4B
-#define PCI_CHIP_RV350_NP               0x4E50
-#define PCI_CHIP_RV350_NQ               0x4E51
-#define PCI_CHIP_RV350_NR               0x4E52
-#define PCI_CHIP_RV350_NS               0x4E53
-#define PCI_CHIP_RV350_NT               0x4E54
-#define PCI_CHIP_RV350_NV               0x4E56
-#define PCI_CHIP_RAGE128PA		0x5041
-#define PCI_CHIP_RAGE128PB		0x5042
-#define PCI_CHIP_RAGE128PC		0x5043
-#define PCI_CHIP_RAGE128PD		0x5044
-#define PCI_CHIP_RAGE128PE		0x5045
-#define PCI_CHIP_RAGE128PF		0x5046
-#define PCI_CHIP_RAGE128PG		0x5047
-#define PCI_CHIP_RAGE128PH		0x5048
-#define PCI_CHIP_RAGE128PI		0x5049
-#define PCI_CHIP_RAGE128PJ		0x504A
-#define PCI_CHIP_RAGE128PK		0x504B
-#define PCI_CHIP_RAGE128PL		0x504C
-#define PCI_CHIP_RAGE128PM		0x504D
-#define PCI_CHIP_RAGE128PN		0x504E
-#define PCI_CHIP_RAGE128PO		0x504F
-#define PCI_CHIP_RAGE128PP		0x5050
-#define PCI_CHIP_RAGE128PQ		0x5051
-#define PCI_CHIP_RAGE128PR		0x5052
-#define PCI_CHIP_RAGE128PS		0x5053
-#define PCI_CHIP_RAGE128PT		0x5054
-#define PCI_CHIP_RAGE128PU		0x5055
-#define PCI_CHIP_RAGE128PV		0x5056
-#define PCI_CHIP_RAGE128PW		0x5057
-#define PCI_CHIP_RAGE128PX		0x5058
-#define PCI_CHIP_RADEON_QD		0x5144
-#define PCI_CHIP_RADEON_QE		0x5145
-#define PCI_CHIP_RADEON_QF		0x5146
-#define PCI_CHIP_RADEON_QG		0x5147
-#define PCI_CHIP_R200_QH		0x5148
-#define PCI_CHIP_R200_QI		0x5149
-#define PCI_CHIP_R200_QJ		0x514A
-#define PCI_CHIP_R200_QK		0x514B
-#define PCI_CHIP_R200_QL		0x514C
-#define PCI_CHIP_R200_QM		0x514D
-#define PCI_CHIP_R200_QN		0x514E
-#define PCI_CHIP_R200_QO		0x514F
-#define PCI_CHIP_RV200_QW		0x5157
-#define PCI_CHIP_RV200_QX		0x5158
-#define PCI_CHIP_RV100_QY		0x5159
-#define PCI_CHIP_RV100_QZ		0x515A
-#define PCI_CHIP_RN50			0x515E
-#define PCI_CHIP_RAGE128RE		0x5245
-#define PCI_CHIP_RAGE128RF		0x5246
-#define PCI_CHIP_RAGE128RG		0x5247
-#define PCI_CHIP_RAGE128RK		0x524B
-#define PCI_CHIP_RAGE128RL		0x524C
-#define PCI_CHIP_RAGE128SE		0x5345
-#define PCI_CHIP_RAGE128SF		0x5346
-#define PCI_CHIP_RAGE128SG		0x5347
-#define PCI_CHIP_RAGE128SH		0x5348
-#define PCI_CHIP_RAGE128SK		0x534B
-#define PCI_CHIP_RAGE128SL		0x534C
-#define PCI_CHIP_RAGE128SM		0x534D
-#define PCI_CHIP_RAGE128SN		0x534E
-#define PCI_CHIP_RAGE128TF		0x5446
-#define PCI_CHIP_RAGE128TL		0x544C
-#define PCI_CHIP_RAGE128TR		0x5452
-#define PCI_CHIP_RAGE128TS		0x5453
-#define PCI_CHIP_RAGE128TT		0x5454
-#define PCI_CHIP_RAGE128TU		0x5455
-#define PCI_CHIP_RV370_5460             0x5460
-#define PCI_CHIP_RV370_5461             0x5461
-#define PCI_CHIP_RV370_5462             0x5462
-#define PCI_CHIP_RV370_5463             0x5463
-#define PCI_CHIP_RV370_5464             0x5464
-#define PCI_CHIP_RV370_5465             0x5465
-#define PCI_CHIP_RV370_5466             0x5466
-#define PCI_CHIP_RV370_5467             0x5467
-#define PCI_CHIP_R423_UH                0x5548
-#define PCI_CHIP_R423_UI                0x5549
-#define PCI_CHIP_R423_UJ                0x554A
-#define PCI_CHIP_R423_UK                0x554B
-#define PCI_CHIP_R423_UQ                0x5551
-#define PCI_CHIP_R423_UR                0x5552
-#define PCI_CHIP_R423_UT                0x5554
-#define PCI_CHIP_MACH64VT		0x5654
-#define PCI_CHIP_MACH64VU		0x5655
-#define PCI_CHIP_MACH64VV		0x5656
-#define PCI_CHIP_RS300_5834		0x5834
-#define PCI_CHIP_RS300_5835		0x5835
-#define PCI_CHIP_RS300_5836		0x5836
-#define PCI_CHIP_RS300_5837		0x5837
-#define PCI_CHIP_RV370_5B60             0x5B60
-#define PCI_CHIP_RV370_5B61             0x5B61
-#define PCI_CHIP_RV370_5B62             0x5B62
-#define PCI_CHIP_RV370_5B63             0x5B63
-#define PCI_CHIP_RV370_5B64             0x5B64
-#define PCI_CHIP_RV370_5B65             0x5B65
-#define PCI_CHIP_RV370_5B66             0x5B66
-#define PCI_CHIP_RV370_5B67             0x5B67
-#define PCI_CHIP_RV280_5960		0x5960
-#define PCI_CHIP_RV280_5961		0x5961
-#define PCI_CHIP_RV280_5962		0x5962
-#define PCI_CHIP_RV280_5964		0x5964
-#define PCI_CHIP_RV280_5C61		0x5C61
-#define PCI_CHIP_RV280_5C63		0x5C63
-#define PCI_CHIP_R423_5D57              0x5D57
-#define PCI_CHIP_RS350_7834             0x7834
-#define PCI_CHIP_RS350_7835             0x7835
diff --git a/drivers/video/ati_radeon_fb.c b/drivers/video/ati_radeon_fb.c
deleted file mode 100644
index 383666781c..0000000000
--- a/drivers/video/ati_radeon_fb.c
+++ /dev/null
@@ -1,761 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * ATI Radeon Video card Framebuffer driver.
- *
- * Copyright 2007 Freescale Semiconductor, Inc.
- * Zhang Wei <wei.zhang@freescale.com>
- * Jason Jin <jason.jin@freescale.com>
- *
- * Some codes of this file is partly ported from Linux kernel
- * ATI video framebuffer driver.
- *
- * Now the driver is tested on below ATI chips:
- *   9200
- *   X300
- *   X700
- */
-
-#include <common.h>
-#include <linux/delay.h>
-
-#include <command.h>
-#include <bios_emul.h>
-#include <env.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <video_fb.h>
-#include "videomodes.h"
-
-#include <radeon.h>
-#include "ati_ids.h"
-#include "ati_radeon_fb.h"
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DPRINT(x...) printf(x)
-#else
-#define DPRINT(x...) do{}while(0)
-#endif
-
-#define MAX_MAPPED_VRAM	(2048*2048*4)
-#define MIN_MAPPED_VRAM	(1024*768*1)
-
-#define RADEON_BUFFER_ALIGN		0x00000fff
-#define SURF_UPPER_BOUND(x,y,bpp)	(((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \
-					  & ~RADEON_BUFFER_ALIGN) - 1)
-#define RADEON_CRT_PITCH(width, bpp)	((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \
-					 ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16))
-
-#define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \
-		(((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16))
-#define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \
-		(((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16))
-#define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \
-		((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16))
-#define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \
-		((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16))
-
-/*#define PCI_VENDOR_ID_ATI*/
-#define PCI_CHIP_RV280_5960		0x5960
-#define PCI_CHIP_RV280_5961		0x5961
-#define PCI_CHIP_RV280_5962		0x5962
-#define PCI_CHIP_RV280_5964		0x5964
-#define PCI_CHIP_RV280_5C63		0x5C63
-#define PCI_CHIP_RV370_5B60		0x5B60
-#define PCI_CHIP_RV380_5657		0x5657
-#define PCI_CHIP_R420_554d		0x554d
-
-static struct pci_device_id ati_radeon_pci_ids[] = {
-	{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5960},
-	{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961},
-	{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962},
-	{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964},
-	{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5C63},
-	{PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60},
-	{PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657},
-	{PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d},
-	{0, 0}
-};
-
-static u16 ati_radeon_id_family_table[][2] = {
-	{PCI_CHIP_RV280_5960, CHIP_FAMILY_RV280},
-	{PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280},
-	{PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280},
-	{PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280},
-	{PCI_CHIP_RV280_5C63, CHIP_FAMILY_RV280},
-	{PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380},
-	{PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380},
-	{PCI_CHIP_R420_554d,  CHIP_FAMILY_R420},
-	{0, 0}
-};
-
-u16 get_radeon_id_family(u16 device)
-{
-	int i;
-	for (i=0; ati_radeon_id_family_table[0][i]; i+=2)
-		if (ati_radeon_id_family_table[0][i] == device)
-			return ati_radeon_id_family_table[0][i + 1];
-	return 0;
-}
-
-struct radeonfb_info *rinfo;
-
-static void radeon_identify_vram(struct radeonfb_info *rinfo)
-{
-	u32 tmp;
-
-	/* framebuffer size */
-	if ((rinfo->family == CHIP_FAMILY_RS100) ||
-		(rinfo->family == CHIP_FAMILY_RS200) ||
-		(rinfo->family == CHIP_FAMILY_RS300)) {
-		u32 tom = INREG(NB_TOM);
-		tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
-
-		radeon_fifo_wait(6);
-		OUTREG(MC_FB_LOCATION, tom);
-		OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
-		OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
-		OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
-
-		/* This is supposed to fix the crtc2 noise problem. */
-		OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
-
-		if ((rinfo->family == CHIP_FAMILY_RS100) ||
-			(rinfo->family == CHIP_FAMILY_RS200)) {
-		/* This is to workaround the asic bug for RMX, some versions
-		   of BIOS dosen't have this register initialized correctly.
-		*/
-			OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
-				~CRTC_H_CUTOFF_ACTIVE_EN);
-		}
-	} else {
-		tmp = INREG(CONFIG_MEMSIZE);
-	}
-
-	/* mem size is bits [28:0], mask off the rest */
-	rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
-
-	/*
-	 * Hack to get around some busted production M6's
-	 * reporting no ram
-	 */
-	if (rinfo->video_ram == 0) {
-		switch (rinfo->pdev.device) {
-		case PCI_CHIP_RADEON_LY:
-		case PCI_CHIP_RADEON_LZ:
-			rinfo->video_ram = 8192 * 1024;
-			break;
-		default:
-			break;
-		}
-	}
-
-	/*
-	 * Now try to identify VRAM type
-	 */
-	if ((rinfo->family >= CHIP_FAMILY_R300) ||
-	    (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
-		rinfo->vram_ddr = 1;
-	else
-		rinfo->vram_ddr = 0;
-
-	tmp = INREG(MEM_CNTL);
-	if (IS_R300_VARIANT(rinfo)) {
-		tmp &=  R300_MEM_NUM_CHANNELS_MASK;
-		switch (tmp) {
-		case 0:  rinfo->vram_width = 64; break;
-		case 1:  rinfo->vram_width = 128; break;
-		case 2:  rinfo->vram_width = 256; break;
-		default: rinfo->vram_width = 128; break;
-		}
-	} else if ((rinfo->family == CHIP_FAMILY_RV100) ||
-		   (rinfo->family == CHIP_FAMILY_RS100) ||
-		   (rinfo->family == CHIP_FAMILY_RS200)){
-		if (tmp & RV100_MEM_HALF_MODE)
-			rinfo->vram_width = 32;
-		else
-			rinfo->vram_width = 64;
-	} else {
-		if (tmp & MEM_NUM_CHANNELS_MASK)
-			rinfo->vram_width = 128;
-		else
-			rinfo->vram_width = 64;
-	}
-
-	/* This may not be correct, as some cards can have half of channel disabled
-	 * ToDo: identify these cases
-	 */
-
-	DPRINT("radeonfb: Found %dk of %s %d bits wide videoram\n",
-	       rinfo->video_ram / 1024,
-	       rinfo->vram_ddr ? "DDR" : "SDRAM",
-	       rinfo->vram_width);
-
-}
-
-static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
-{
-	int i;
-
-	radeon_fifo_wait(20);
-
-#if 0
-	/* Workaround from XFree */
-	if (rinfo->is_mobility) {
-		/* A temporal workaround for the occational blanking on certain laptop
-		 * panels. This appears to related to the PLL divider registers
-		 * (fail to lock?). It occurs even when all dividers are the same
-		 * with their old settings. In this case we really don't need to
-		 * fiddle with PLL registers. By doing this we can avoid the blanking
-		 * problem with some panels.
-		 */
-		if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
-		    (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
-					  (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
-			/* We still have to force a switch to selected PPLL div thanks to
-			 * an XFree86 driver bug which will switch it away in some cases
-			 * even when using UseFDev */
-			OUTREGP(CLOCK_CNTL_INDEX,
-				mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
-				~PPLL_DIV_SEL_MASK);
-			radeon_pll_errata_after_index(rinfo);
-			radeon_pll_errata_after_data(rinfo);
-			return;
-		}
-	}
-#endif
-	if(rinfo->pdev.device == PCI_CHIP_RV370_5B60) return;
-
-	/* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
-	OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
-
-	/* Reset PPLL & enable atomic update */
-	OUTPLLP(PPLL_CNTL,
-		PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
-		~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
-
-	/* Switch to selected PPLL divider */
-	OUTREGP(CLOCK_CNTL_INDEX,
-		mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
-		~PPLL_DIV_SEL_MASK);
-
-	/* Set PPLL ref. div */
-	if (rinfo->family == CHIP_FAMILY_R300 ||
-	    rinfo->family == CHIP_FAMILY_RS300 ||
-	    rinfo->family == CHIP_FAMILY_R350 ||
-	    rinfo->family == CHIP_FAMILY_RV350) {
-		if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
-			/* When restoring console mode, use saved PPLL_REF_DIV
-			 * setting.
-			 */
-			OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
-		} else {
-			/* R300 uses ref_div_acc field as real ref divider */
-			OUTPLLP(PPLL_REF_DIV,
-				(mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
-				~R300_PPLL_REF_DIV_ACC_MASK);
-		}
-	} else
-		OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
-
-	/* Set PPLL divider 3 & post divider*/
-	OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
-	OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
-
-	/* Write update */
-	while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
-		;
-	OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
-
-	/* Wait read update complete */
-	/* FIXME: Certain revisions of R300 can't recover here.  Not sure of
-	   the cause yet, but this workaround will mask the problem for now.
-	   Other chips usually will pass at the very first test, so the
-	   workaround shouldn't have any effect on them. */
-	for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
-		;
-
-	OUTPLL(HTOTAL_CNTL, 0);
-
-	/* Clear reset & atomic update */
-	OUTPLLP(PPLL_CNTL, 0,
-		~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
-
-	/* We may want some locking ... oh well */
-	udelay(5000);
-
-	/* Switch back VCLK source to PPLL */
-	OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
-}
-
-typedef struct {
-	u16 reg;
-	u32 val;
-} reg_val;
-
-#if 0	/* unused ? -> scheduled for removal */
-/* these common regs are cleared before mode setting so they do not
- * interfere with anything
- */
-static reg_val common_regs[] = {
-	{ OVR_CLR, 0 },
-	{ OVR_WID_LEFT_RIGHT, 0 },
-	{ OVR_WID_TOP_BOTTOM, 0 },
-	{ OV0_SCALE_CNTL, 0 },
-	{ SUBPIC_CNTL, 0 },
-	{ VIPH_CONTROL, 0 },
-	{ I2C_CNTL_1, 0 },
-	{ GEN_INT_CNTL, 0 },
-	{ CAP0_TRIG_CNTL, 0 },
-	{ CAP1_TRIG_CNTL, 0 },
-};
-#endif /* 0 */
-
-void radeon_setmode(void)
-{
-	struct radeon_regs *mode = malloc(sizeof(struct radeon_regs));
-
-	mode->crtc_gen_cntl = 0x03000200;
-	mode->crtc_ext_cntl = 0x00008048;
-	mode->dac_cntl = 0xff002100;
-	mode->crtc_h_total_disp = 0x4f0063;
-	mode->crtc_h_sync_strt_wid = 0x8c02a2;
-	mode->crtc_v_total_disp = 0x01df020c;
-	mode->crtc_v_sync_strt_wid = 0x8201ea;
-	mode->crtc_pitch = 0x00500050;
-
-	OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
-	OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
-		~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
-	OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
-	OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
-	OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
-	OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
-	OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
-	OUTREG(CRTC_OFFSET, 0);
-	OUTREG(CRTC_OFFSET_CNTL, 0);
-	OUTREG(CRTC_PITCH, mode->crtc_pitch);
-
-	mode->clk_cntl_index = 0x300;
-	mode->ppll_ref_div = 0xc;
-	mode->ppll_div_3 = 0x00030059;
-
-	radeon_write_pll_regs(rinfo, mode);
-}
-
-static void set_pal(void)
-{
-	int idx, val = 0;
-
-	for (idx = 0; idx < 256; idx++) {
-		OUTREG8(PALETTE_INDEX, idx);
-		OUTREG(PALETTE_DATA, val);
-		val += 0x00010101;
-	}
-}
-
-void radeon_setmode_9200(int vesa_idx, int bpp)
-{
-	struct radeon_regs *mode = malloc(sizeof(struct radeon_regs));
-
-	mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN;
-	mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON;
-	mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN;
-	mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN;
-
-	switch (bpp) {
-	case 24:
-		mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */
-#if defined(__BIG_ENDIAN)
-		mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP;
-		mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP;
-#endif
-		break;
-	case 16:
-		mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */
-#if defined(__BIG_ENDIAN)
-		mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP;
-		mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP;
-#endif
-		break;
-	default:
-		mode->crtc_gen_cntl |= 0x2 << 8; /* palette */
-		mode->surface_cntl = 0x00000000;
-		break;
-	}
-
-	switch (vesa_idx) {
-	case RES_MODE_1280x1024:
-		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280);
-		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024);
-		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3);
-#if defined(CONFIG_RADEON_VREFRESH_75HZ)
-		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18);
-		mode->ppll_div_3 = 0x00010078;
-#else /* default @ 60 Hz */
-		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14);
-		mode->ppll_div_3 = 0x00010060;
-#endif
-		/*
-		 * for this mode pitch expands to the same value for 32, 16 and 8 bpp,
-		 * so we set it here once only.
-		 */
-		mode->crtc_pitch = RADEON_CRT_PITCH(1280,32);
-		switch (bpp) {
-		case 24:
-			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16);
-			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32);
-			break;
-		case 16:
-			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16);
-			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16);
-			break;
-		default: /* 8 bpp */
-			mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16);
-			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8);
-			break;
-		}
-		break;
-	case RES_MODE_1024x768:
-#if defined(CONFIG_RADEON_VREFRESH_75HZ)
-		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024);
-		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12);
-		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768);
-		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3);
-		mode->ppll_div_3 = 0x0002008c;
-#else /* @ 60 Hz */
-		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024);
-		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL;
-		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768);
-		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL;
-		mode->ppll_div_3 = 0x00020074;
-#endif
-		/* also same pitch value for 32, 16 and 8 bpp */
-		mode->crtc_pitch = RADEON_CRT_PITCH(1024,32);
-		switch (bpp) {
-		case 24:
-			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16);
-			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32);
-			break;
-		case 16:
-			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16);
-			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16);
-			break;
-		default: /* 8 bpp */
-			mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16);
-			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8);
-			break;
-		}
-		break;
-	case RES_MODE_800x600:
-		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800);
-#if defined(CONFIG_RADEON_VREFRESH_75HZ)
-		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10);
-		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600);
-		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3);
-		mode->ppll_div_3 = 0x000300b0;
-#else /* @ 60 Hz */
-		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16);
-		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600);
-		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4);
-		mode->ppll_div_3 = 0x0003008e;
-#endif
-		switch (bpp) {
-		case 24:
-			mode->crtc_pitch = RADEON_CRT_PITCH(832,32);
-			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16);
-			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32);
-			break;
-		case 16:
-			mode->crtc_pitch = RADEON_CRT_PITCH(896,16);
-			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16);
-			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16);
-			break;
-		default: /* 8 bpp */
-			mode->crtc_pitch = RADEON_CRT_PITCH(1024,8);
-			mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16);
-			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8);
-			break;
-		}
-		break;
-	default: /* RES_MODE_640x480 */
-#if defined(CONFIG_RADEON_VREFRESH_75HZ)
-		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640);
-		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL;
-		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480);
-		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL;
-		mode->ppll_div_3 = 0x00030070;
-#else /* @ 60 Hz */
-		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640);
-		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL;
-		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480);
-		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL;
-		mode->ppll_div_3 = 0x00030059;
-#endif
-		/* also same pitch value for 32, 16 and 8 bpp */
-		mode->crtc_pitch = RADEON_CRT_PITCH(640,32);
-		switch (bpp) {
-		case 24:
-			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16);
-			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32);
-			break;
-		case 16:
-			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16);
-			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16);
-			break;
-		default: /* 8 bpp */
-			mode->crtc_offset_cntl = 0x00000000;
-			break;
-		}
-		break;
-	}
-
-	OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
-	OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
-		(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
-	OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
-	OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
-	OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
-	OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
-	OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
-	OUTREG(CRTC_OFFSET, 0);
-	OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl);
-	OUTREG(CRTC_PITCH, mode->crtc_pitch);
-	OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
-
-	mode->clk_cntl_index = 0x300;
-	mode->ppll_ref_div = 0xc;
-
-	radeon_write_pll_regs(rinfo, mode);
-
-	OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
-		~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
-	OUTREG(SURFACE0_INFO, mode->surf_info[0]);
-	OUTREG(SURFACE0_LOWER_BOUND, 0);
-	OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]);
-	OUTREG(SURFACE_CNTL, mode->surface_cntl);
-
-	if (bpp > 8)
-		set_pal();
-
-	free(mode);
-}
-
-#include "../bios_emulator/include/biosemu.h"
-
-int radeon_probe(struct radeonfb_info *rinfo)
-{
-	pci_dev_t pdev;
-	u16 did;
-
-	pdev = pci_find_devices(ati_radeon_pci_ids, 0);
-
-	if (pdev != -1) {
-		pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
-		printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n",
-				PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff,
-				(pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
-
-		strcpy(rinfo->name, "ATI Radeon");
-		rinfo->pdev.vendor = PCI_VENDOR_ID_ATI;
-		rinfo->pdev.device = did;
-		rinfo->family = get_radeon_id_family(rinfo->pdev.device);
-		pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
-				&rinfo->fb_base_bus);
-		pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2,
-				&rinfo->mmio_base_bus);
-		rinfo->fb_base_bus &= 0xfffff000;
-		rinfo->mmio_base_bus &= ~0x04;
-
-		rinfo->mmio_base = pci_bus_to_virt(pdev, rinfo->mmio_base_bus,
-					PCI_REGION_MEM, 0, MAP_NOCACHE);
-		DPRINT("rinfo->mmio_base = 0x%p bus=0x%x\n",
-		       rinfo->mmio_base, rinfo->mmio_base_bus);
-		rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
-		DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base);
-		/* PostBIOS with x86 emulater */
-		if (!BootVideoCardBIOS(pdev, NULL, 0))
-			return -1;
-
-		/*
-		 * Check for errata
-		 * (These will be added in the future for the chipfamily
-		 * R300, RV200, RS200, RV100, RS100.)
-		 */
-
-		/* Get VRAM size and type */
-		radeon_identify_vram(rinfo);
-
-		rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM,
-				rinfo->video_ram);
-		rinfo->fb_base = pci_bus_to_virt(pdev, rinfo->fb_base_bus,
-					PCI_REGION_MEM, 0, MAP_NOCACHE);
-		DPRINT("Radeon: framebuffer base address 0x%08x, "
-		       "bus address 0x%08x\n"
-		       "MMIO base address 0x%08x, bus address 0x%08x, "
-		       "framebuffer local base 0x%08x.\n ",
-		       (u32)rinfo->fb_base, rinfo->fb_base_bus,
-		       (u32)rinfo->mmio_base, rinfo->mmio_base_bus,
-		       rinfo->fb_local_base);
-		return 0;
-	}
-	return -1;
-}
-
-/*
- * The Graphic Device
- */
-GraphicDevice ctfb;
-
-#define CURSOR_SIZE	0x1000	/* in KByte for HW Cursor */
-#define PATTERN_ADR	(pGD->dprBase + CURSOR_SIZE)	/* pattern Memory after Cursor Memory */
-#define PATTERN_SIZE	8*8*4	/* 4 Bytes per Pixel 8 x 8 Pixel */
-#define ACCELMEMORY	(CURSOR_SIZE + PATTERN_SIZE)	/* reserved Memory for BITBlt and hw cursor */
-
-void *video_hw_init(void)
-{
-	GraphicDevice *pGD = (GraphicDevice *) & ctfb;
-	u32 *vm;
-	char *penv;
-	unsigned long t1, hsynch, vsynch;
-	int bits_per_pixel, i, tmp, vesa_idx = 0, videomode;
-	struct ctfb_res_modes *res_mode;
-	struct ctfb_res_modes var_mode;
-
-	rinfo = malloc(sizeof(struct radeonfb_info));
-
-	printf("Video: ");
-	if(radeon_probe(rinfo)) {
-		printf("No radeon video card found!\n");
-		return NULL;
-	}
-
-	tmp = 0;
-
-	videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
-	/* get video mode via environment */
-	penv = env_get("videomode");
-	if (penv) {
-		/* deceide if it is a string */
-		if (penv[0] <= '9') {
-			videomode = (int)hextoul(penv, NULL);
-			tmp = 1;
-		}
-	} else {
-		tmp = 1;
-	}
-	if (tmp) {
-		/* parameter are vesa modes */
-		/* search params */
-		for (i = 0; i < VESA_MODES_COUNT; i++) {
-			if (vesa_modes[i].vesanr == videomode)
-				break;
-		}
-		if (i == VESA_MODES_COUNT) {
-			printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE);
-			i = 0;
-		}
-		res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex];
-		bits_per_pixel = vesa_modes[i].bits_per_pixel;
-		vesa_idx = vesa_modes[i].resindex;
-	} else {
-		res_mode = (struct ctfb_res_modes *) &var_mode;
-		bits_per_pixel = video_get_params (res_mode, penv);
-	}
-
-	/* calculate hsynch and vsynch freq (info only) */
-	t1 = (res_mode->left_margin + res_mode->xres +
-	      res_mode->right_margin + res_mode->hsync_len) / 8;
-	t1 *= 8;
-	t1 *= res_mode->pixclock;
-	t1 /= 1000;
-	hsynch = 1000000000L / t1;
-	t1 *= (res_mode->upper_margin + res_mode->yres +
-	       res_mode->lower_margin + res_mode->vsync_len);
-	t1 /= 1000;
-	vsynch = 1000000000L / t1;
-
-	/* fill in Graphic device struct */
-	sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
-		 res_mode->yres, bits_per_pixel, (hsynch / 1000),
-		 (vsynch / 1000));
-	printf ("%s\n", pGD->modeIdent);
-	pGD->winSizeX = res_mode->xres;
-	pGD->winSizeY = res_mode->yres;
-	pGD->plnSizeX = res_mode->xres;
-	pGD->plnSizeY = res_mode->yres;
-
-	switch (bits_per_pixel) {
-	case 24:
-		pGD->gdfBytesPP = 4;
-		pGD->gdfIndex = GDF_32BIT_X888RGB;
-		if (res_mode->xres == 800) {
-			pGD->winSizeX = 832;
-			pGD->plnSizeX = 832;
-		}
-		break;
-	case 16:
-		pGD->gdfBytesPP = 2;
-		pGD->gdfIndex = GDF_16BIT_565RGB;
-		if (res_mode->xres == 800) {
-			pGD->winSizeX = 896;
-			pGD->plnSizeX = 896;
-		}
-		break;
-	default:
-		if (res_mode->xres == 800) {
-			pGD->winSizeX = 1024;
-			pGD->plnSizeX = 1024;
-		}
-		pGD->gdfBytesPP = 1;
-		pGD->gdfIndex = GDF__8BIT_INDEX;
-		break;
-	}
-
-	pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
-	pGD->pciBase = (unsigned int)rinfo->fb_base;
-	pGD->frameAdrs = (unsigned int)rinfo->fb_base;
-	pGD->memSize = 64 * 1024 * 1024;
-
-	/* Cursor Start Address */
-	pGD->dprBase = (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) +
-		(unsigned int)rinfo->fb_base;
-	if ((pGD->dprBase & 0x0fff) != 0) {
-		/* allign it */
-		pGD->dprBase &= 0xfffff000;
-		pGD->dprBase += 0x00001000;
-	}
-	DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
-		PATTERN_ADR);
-	pGD->vprBase = (unsigned int)rinfo->fb_base;	/* Dummy */
-	pGD->cprBase = (unsigned int)rinfo->fb_base;	/* Dummy */
-	/* set up Hardware */
-
-	/* Clear video memory (only visible screen area) */
-	i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4;
-	vm = (unsigned int *) pGD->pciBase;
-	while (i--)
-		*vm++ = 0;
-	/*SetDrawingEngine (bits_per_pixel);*/
-
-	if (rinfo->family == CHIP_FAMILY_RV280)
-		radeon_setmode_9200(vesa_idx, bits_per_pixel);
-	else
-		radeon_setmode();
-
-	return ((void *) pGD);
-}
-
-void video_set_lut (unsigned int index,	/* color number */
-	       unsigned char r,	/* red */
-	       unsigned char g,	/* green */
-	       unsigned char b	/* blue */
-	       )
-{
-	OUTREG(PALETTE_INDEX, index);
-	OUTREG(PALETTE_DATA, (r << 16) | (g << 8) | b);
-}
diff --git a/drivers/video/ati_radeon_fb.h b/drivers/video/ati_radeon_fb.h
deleted file mode 100644
index 9dd638bb9e..0000000000
--- a/drivers/video/ati_radeon_fb.h
+++ /dev/null
@@ -1,282 +0,0 @@
-#ifndef __ATI_RADEON_FB_H
-#define __ATI_RADEON_FB_H
-
-/***************************************************************
- * Most of the definitions here are adapted right from XFree86 *
- ***************************************************************/
-
-/*
- * Chip families. Must fit in the low 16 bits of a long word
- */
-enum radeon_family {
-	CHIP_FAMILY_UNKNOW,
-	CHIP_FAMILY_LEGACY,
-	CHIP_FAMILY_RADEON,
-	CHIP_FAMILY_RV100,
-	CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
-	CHIP_FAMILY_RV200,
-	CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
-				 RS250 (IGP 7000) */
-	CHIP_FAMILY_R200,
-	CHIP_FAMILY_RV250,
-	CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
-	CHIP_FAMILY_RV280,
-	CHIP_FAMILY_R300,
-	CHIP_FAMILY_R350,
-	CHIP_FAMILY_RV350,
-	CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
-	CHIP_FAMILY_R420,     /* R420/R423/M18 */
-	CHIP_FAMILY_LAST,
-};
-
-#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100)  || \
-				 ((rinfo)->family == CHIP_FAMILY_RV200)  || \
-				 ((rinfo)->family == CHIP_FAMILY_RS100)  || \
-				 ((rinfo)->family == CHIP_FAMILY_RS200)  || \
-				 ((rinfo)->family == CHIP_FAMILY_RV250)  || \
-				 ((rinfo)->family == CHIP_FAMILY_RV280)  || \
-				 ((rinfo)->family == CHIP_FAMILY_RS300))
-
-#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300)  || \
-				((rinfo)->family == CHIP_FAMILY_RV350) || \
-				((rinfo)->family == CHIP_FAMILY_R350)  || \
-				((rinfo)->family == CHIP_FAMILY_RV380) || \
-				((rinfo)->family == CHIP_FAMILY_R420))
-
-struct radeonfb_info {
-	char name[20];
-
-	struct pci_device_id	pdev;
-	u16			family;
-
-	u32			fb_base_bus;
-	u32			mmio_base_bus;
-
-	void			*mmio_base;
-	void			*fb_base;
-
-	u32			video_ram;
-	u32			mapped_vram;
-	int			vram_width;
-	int			vram_ddr;
-
-	u32			fb_local_base;
-};
-
-#define INREG8(addr)		readb((rinfo->mmio_base)+addr)
-#define OUTREG8(addr,val)	writeb(val, (rinfo->mmio_base)+addr)
-#define INREG16(addr)		readw((rinfo->mmio_base)+addr)
-#define OUTREG16(addr,val)	writew(val, (rinfo->mmio_base)+addr)
-#define INREG(addr)		readl((rinfo->mmio_base)+addr)
-#define OUTREG(addr,val)	writel(val, (rinfo->mmio_base)+addr)
-
-static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
-		       u32 val, u32 mask)
-{
-	unsigned int tmp;
-
-	tmp = INREG(addr);
-	tmp &= (mask);
-	tmp |= (val);
-	OUTREG(addr, tmp);
-}
-
-#define OUTREGP(addr,val,mask)	_OUTREGP(rinfo, addr, val,mask)
-
-/*
- * 2D Engine helper routines
- */
-static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
-{
-	int i;
-
-	/* initiate flush */
-	OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
-		~RB2D_DC_FLUSH_ALL);
-
-	for (i=0; i < 2000000; i++) {
-		if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
-			return;
-		udelay(1);
-	}
-	printf("radeonfb: Flush Timeout !\n");
-}
-
-static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
-{
-	int i;
-
-	for (i=0; i<2000000; i++) {
-		if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
-			return;
-		udelay(1);
-	}
-	printf("radeonfb: FIFO Timeout !\n");
-}
-
-static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
-{
-	int i;
-
-	/* ensure FIFO is empty before waiting for idle */
-	_radeon_fifo_wait (rinfo, 64);
-
-	for (i=0; i<2000000; i++) {
-		if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
-			radeon_engine_flush (rinfo);
-			return;
-		}
-		udelay(1);
-	}
-	printf("radeonfb: Idle Timeout !\n");
-}
-
-#define radeon_engine_idle()		_radeon_engine_idle(rinfo)
-#define radeon_fifo_wait(entries)	_radeon_fifo_wait(rinfo,entries)
-#define radeon_msleep(ms)		_radeon_msleep(rinfo,ms)
-
-/*
- * This structure contains the various registers manipulated by this
- * driver for setting or restoring a mode. It's mostly copied from
- * XFree's RADEONSaveRec structure. A few chip settings might still be
- * tweaked without beeing reflected or saved in these registers though
- */
-struct radeon_regs {
-	/* Common registers */
-	u32		ovr_clr;
-	u32		ovr_wid_left_right;
-	u32		ovr_wid_top_bottom;
-	u32		ov0_scale_cntl;
-	u32		mpp_tb_config;
-	u32		mpp_gp_config;
-	u32		subpic_cntl;
-	u32		viph_control;
-	u32		i2c_cntl_1;
-	u32		gen_int_cntl;
-	u32		cap0_trig_cntl;
-	u32		cap1_trig_cntl;
-	u32		bus_cntl;
-	u32		surface_cntl;
-	u32		bios_5_scratch;
-
-	/* Other registers to save for VT switches or driver load/unload */
-	u32		dp_datatype;
-	u32		rbbm_soft_reset;
-	u32		clock_cntl_index;
-	u32		amcgpio_en_reg;
-	u32		amcgpio_mask;
-
-	/* Surface/tiling registers */
-	u32		surf_lower_bound[8];
-	u32		surf_upper_bound[8];
-	u32		surf_info[8];
-
-	/* CRTC registers */
-	u32		crtc_gen_cntl;
-	u32		crtc_ext_cntl;
-	u32		dac_cntl;
-	u32		crtc_h_total_disp;
-	u32		crtc_h_sync_strt_wid;
-	u32		crtc_v_total_disp;
-	u32		crtc_v_sync_strt_wid;
-	u32		crtc_offset;
-	u32		crtc_offset_cntl;
-	u32		crtc_pitch;
-	u32		disp_merge_cntl;
-	u32		grph_buffer_cntl;
-	u32		crtc_more_cntl;
-
-	/* CRTC2 registers */
-	u32		crtc2_gen_cntl;
-	u32		dac2_cntl;
-	u32		disp_output_cntl;
-	u32		disp_hw_debug;
-	u32		disp2_merge_cntl;
-	u32		grph2_buffer_cntl;
-	u32		crtc2_h_total_disp;
-	u32		crtc2_h_sync_strt_wid;
-	u32		crtc2_v_total_disp;
-	u32		crtc2_v_sync_strt_wid;
-	u32		crtc2_offset;
-	u32		crtc2_offset_cntl;
-	u32		crtc2_pitch;
-
-	/* Flat panel regs */
-	u32		fp_crtc_h_total_disp;
-	u32		fp_crtc_v_total_disp;
-	u32		fp_gen_cntl;
-	u32		fp2_gen_cntl;
-	u32		fp_h_sync_strt_wid;
-	u32		fp2_h_sync_strt_wid;
-	u32		fp_horz_stretch;
-	u32		fp_panel_cntl;
-	u32		fp_v_sync_strt_wid;
-	u32		fp2_v_sync_strt_wid;
-	u32		fp_vert_stretch;
-	u32		lvds_gen_cntl;
-	u32		lvds_pll_cntl;
-	u32		tmds_crc;
-	u32		tmds_transmitter_cntl;
-
-	/* Computed values for PLL */
-	u32		dot_clock_freq;
-	int		feedback_div;
-	int		post_div;
-
-	/* PLL registers */
-	u32		ppll_div_3;
-	u32		ppll_ref_div;
-	u32		vclk_ecp_cntl;
-	u32		clk_cntl_index;
-
-	/* Computed values for PLL2 */
-	u32		dot_clock_freq_2;
-	int		feedback_div_2;
-	int		post_div_2;
-
-	/* PLL2 registers */
-	u32		p2pll_ref_div;
-	u32		p2pll_div_0;
-	u32		htotal_cntl2;
-
-	/* Palette */
-	int		palette_valid;
-};
-
-static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
-{
-	u32 data;
-
-	OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
-	/* radeon_pll_errata_after_index(rinfo); */
-	data = INREG(CLOCK_CNTL_DATA);
-	/* radeon_pll_errata_after_data(rinfo); */
-	return data;
-}
-
-static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
-			    u32 val)
-{
-
-	OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
-	/* radeon_pll_errata_after_index(rinfo); */
-	OUTREG(CLOCK_CNTL_DATA, val);
-	/* radeon_pll_errata_after_data(rinfo); */
-}
-
-static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
-			     u32 val, u32 mask)
-{
-	unsigned int tmp;
-
-	tmp  = __INPLL(rinfo, index);
-	tmp &= (mask);
-	tmp |= (val);
-	__OUTPLL(rinfo, index, tmp);
-}
-
-#define INPLL(addr)			__INPLL(rinfo, addr)
-#define OUTPLL(index, val)		__OUTPLL(rinfo, index, val)
-#define OUTPLLP(index, val, mask)	__OUTPLLP(rinfo, index, val, mask)
-
-#endif
diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c
index 67f5266164..21ade8d93c 100644
--- a/drivers/video/pxa_lcd.c
+++ b/drivers/video/pxa_lcd.c
@@ -199,72 +199,6 @@ vidinfo_t panel_info = {
 
 /*----------------------------------------------------------------------*/
 
-#ifdef CONFIG_ACX517AKN
-
-# define LCD_BPP	LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x003008f9
-# define REG_LCCR3	0x03700006
-
-vidinfo_t panel_info = {
-	.vl_col		= 320,
-	.vl_row		= 320,
-	.vl_width	= 320,
-	.vl_height	= 320,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_LOW,
-	.vl_hsp		= CONFIG_SYS_LOW,
-	.vl_vsp		= CONFIG_SYS_LOW,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 1,
-	.vl_hpw		= 0x04,
-	.vl_blw		= 0x1c,
-	.vl_elw		= 0x08,
-	.vl_vpw		= 0x01,
-	.vl_bfw		= 0x07,
-	.vl_efw		= 0x08,
-};
-#endif /* CONFIG_ACX517AKN */
-
-#ifdef CONFIG_ACX544AKN
-
-# define LCD_BPP	LCD_COLOR16
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x003008f9
-# define REG_LCCR3	0x04700007 /* 16bpp */
-
-vidinfo_t panel_info = {
-	.vl_col		= 320,
-	.vl_row		= 320,
-	.vl_width	= 320,
-	.vl_height	= 320,
-	.vl_clkp	= CONFIG_SYS_LOW,
-	.vl_oep		= CONFIG_SYS_LOW,
-	.vl_hsp		= CONFIG_SYS_LOW,
-	.vl_vsp		= CONFIG_SYS_LOW,
-	.vl_dp		= CONFIG_SYS_LOW,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 0,
-	.vl_clor	= 1,
-	.vl_tft		= 1,
-	.vl_hpw		= 0x05,
-	.vl_blw		= 0x13,
-	.vl_elw		= 0x08,
-	.vl_vpw		= 0x02,
-	.vl_bfw		= 0x07,
-	.vl_efw		= 0x05,
-};
-#endif /* CONFIG_ACX544AKN */
-
-/*----------------------------------------------------------------------*/
-
 #ifdef CONFIG_LQ038J7DH53
 
 # define LCD_BPP	LCD_COLOR8
@@ -295,7 +229,7 @@ vidinfo_t panel_info = {
 	.vl_bfw		= 0x04,
 	.vl_efw		= 0x01,
 };
-#endif /* CONFIG_ACX517AKN */
+#endif /* CONFIG_LQ038J7DH53 */
 
 /*----------------------------------------------------------------------*/
author	Tom Rini <trini@konsulko.com>	2021-08-30 23:44:54 +0300
committer	Tom Rini <trini@konsulko.com>	2021-08-30 23:56:54 +0300
commit	a85a8e63c5cf8ccb3905eb5982bf8bdcb2978557 (patch)
tree	b9feab308105519bdac26729cee734ef49bb62f2 /drivers
parent	9b0583a839ab8b086b65b4762769abbe048a524d (diff)
parent	809c4f242f6c05f67a097ace0098c5bc1dfebdfb (diff)
download	u-boot-a85a8e63c5cf8ccb3905eb5982bf8bdcb2978557.tar.xz