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author | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2020-05-25 14:39:53 +0300 |
---|---|---|
committer | Matthias Brugger <mbrugger@suse.com> | 2020-07-09 16:46:12 +0300 |
commit | b6687e19f9d3fdd33e76991df3dfcba60961ce35 (patch) | |
tree | a1d307d9910c05fe42a74b24cbb5aa83c91c1fb9 /drivers | |
parent | 8e2ab05000ab91daea63022665d2b0c86f5cba3c (diff) | |
download | u-boot-b6687e19f9d3fdd33e76991df3dfcba60961ce35.tar.xz |
pci: Move some PCIe register offset definitions to a common header
Some PCI Express register offsets are currently defined in multiple
drivers, move them to a common header to avoid re-definitions and
as a pre-requisite for adding new PCIe driver.
While at it replace some spaces with tabs.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/pci/pci-rcar-gen3.c | 8 | ||||
-rw-r--r-- | drivers/pci/pcie_intel_fpga.c | 3 |
2 files changed, 0 insertions, 11 deletions
diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index df7b37a592..1f51854ccc 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -118,14 +118,6 @@ #define RCAR_PCI_MAX_RESOURCES 4 #define MAX_NR_INBOUND_MAPS 6 -#define PCI_EXP_FLAGS 2 /* Capabilities register */ -#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ -#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ -#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ -#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ -#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ -#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ - enum { RCAR_PCI_ACCESS_READ, RCAR_PCI_ACCESS_WRITE, diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index aa1903e547..9f102c64c6 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -67,9 +67,6 @@ #define IS_ROOT_PORT(pcie, bdf) \ ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) -#define PCI_EXP_LNKSTA 18 /* Link Status */ -#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ - /** * struct intel_fpga_pcie - Intel FPGA PCIe controller state * @bus: Pointer to the PCI bus |