Merge tag 'ti-v2020.04-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti

- DFU boot support for J721e
- I2C support for J721e
- GPIO support for J721e
- Android boot image updates on AM57XX
- OMAP watchdog fixes

3 files changed, 44 insertions, 26 deletions

diff --git a/drivers/gpio/da8xx_gpio.c b/drivers/gpio/da8xx_gpio.c
index bd5a366aef..ac88f0ca8d 100644
--- a/drivers/gpio/da8xx_gpio.c
+++ b/drivers/gpio/da8xx_gpio.c
@@ -434,7 +434,7 @@ int gpio_set_value(unsigned int gpio, int value)
 static struct davinci_gpio *davinci_get_gpio_bank(struct udevice *dev, unsigned int offset)
 {
 	struct davinci_gpio_bank *bank = dev_get_priv(dev);
-	unsigned int addr;
+	unsigned long addr;
 
 	/*
 	 * The device tree is not broken into banks but the infrastructure is
@@ -535,6 +535,7 @@ static int davinci_gpio_probe(struct udevice *dev)
 static const struct udevice_id davinci_gpio_ids[] = {
 	{ .compatible = "ti,dm6441-gpio" },
 	{ .compatible = "ti,k2g-gpio" },
+	{ .compatible = "ti,keystone-gpio" },
 	{ }
 };
 
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index 07a3356b3c..5c2944067b 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -15,8 +15,7 @@
  *
  * TODO:
  * 1. Support PCA957X_TYPE
- * 2. Support 24 gpio pins
- * 3. Support Polarity Inversion
+ * 2. Support Polarity Inversion
  */
 
 #include <common.h>
@@ -118,6 +117,10 @@ static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val)
 		ret = dm_i2c_read(dev, reg, val, 1);
 	} else if (info->gpio_count <= 16) {
 		ret = dm_i2c_read(dev, reg << 1, val, info->bank_count);
+	} else if (info->gpio_count <= 24) {
+		/* Auto increment */
+		ret = dm_i2c_read(dev, (reg << 2) | 0x80, val,
+				  info->bank_count);
 	} else if (info->gpio_count == 40) {
 		/* Auto increment */
 		ret = dm_i2c_read(dev, (reg << 3) | 0x80, val,
@@ -139,6 +142,10 @@ static int pca953x_write_regs(struct udevice *dev, int reg, u8 *val)
 		ret = dm_i2c_write(dev, reg, val, 1);
 	} else if (info->gpio_count <= 16) {
 		ret = dm_i2c_write(dev, reg << 1, val, info->bank_count);
+	} else if (info->gpio_count <= 24) {
+		/* Auto increment */
+		ret = dm_i2c_write(dev, (reg << 2) | 0x80, val,
+				   info->bank_count);
 	} else if (info->gpio_count == 40) {
 		/* Auto increment */
 		ret = dm_i2c_write(dev, (reg << 3) | 0x80, val, info->bank_count);
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
index 284cfbb2a8..5199d914ed 100644
--- a/drivers/watchdog/omap_wdt.c
+++ b/drivers/watchdog/omap_wdt.c
@@ -150,24 +150,24 @@ static int omap3_wdt_reset(struct udevice *dev)
 {
 	struct omap3_wdt_priv *priv = dev_get_priv(dev);
 
-/*
- * Somebody just triggered watchdog reset and write to WTGR register
- * is in progress. It is resetting right now, no need to trigger it
- * again
- */
+	/*
+	 * Somebody just triggered watchdog reset and write to WTGR register
+	 * is in progress. It is resetting right now, no need to trigger it
+	 * again
+	 */
 	if ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WTGR)
 		return 0;
 
 	priv->wdt_trgr_pattern = ~(priv->wdt_trgr_pattern);
 	writel(priv->wdt_trgr_pattern, &priv->regs->wdtwtgr);
-/*
- * Don't wait for posted write to complete, i.e. don't check
- * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
- * WTGR register outside of this func, and if entering it
- * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
- * was just triggered. This prevents us from wasting time in busy
- * polling of WDT_WWPS_PEND_WTGR bit.
- */
+	/*
+	 * Don't wait for posted write to complete, i.e. don't check
+	 * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
+	 * WTGR register outside of this func, and if entering it
+	 * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
+	 * was just triggered. This prevents us from wasting time in busy
+	 * polling of WDT_WWPS_PEND_WTGR bit.
+	 */
 	return 0;
 }
 
@@ -175,7 +175,7 @@ static int omap3_wdt_stop(struct udevice *dev)
 {
 	struct omap3_wdt_priv *priv = dev_get_priv(dev);
 
-/* disable watchdog */
+	/* disable watchdog */
 	writel(0xAAAA, &priv->regs->wdtwspr);
 	while (readl(&priv->regs->wdtwwps) != 0x0)
 		;
@@ -188,29 +188,29 @@ static int omap3_wdt_stop(struct udevice *dev)
 static int omap3_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
 {
 	struct omap3_wdt_priv *priv = dev_get_priv(dev);
-	u32 pre_margin = GET_WLDR_VAL(timeout_ms);
-/*
- * Make sure the watchdog is disabled. This is unfortunately required
- * because writing to various registers with the watchdog running has no
- * effect.
- */
+	u32 pre_margin = GET_WLDR_VAL(timeout_ms / 1000);
+	/*
+	 * Make sure the watchdog is disabled. This is unfortunately required
+	 * because writing to various registers with the watchdog running has
+	 * no effect.
+	 */
 	omap3_wdt_stop(dev);
 
-/* initialize prescaler */
+	/* initialize prescaler */
 	while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WCLR)
 		;
 
 	writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &priv->regs->wdtwclr);
 	while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WCLR)
 		;
-/* just count up at 32 KHz */
+	/* just count up at 32 KHz */
 	while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WLDR)
 		;
 
 	writel(pre_margin, &priv->regs->wdtwldr);
 	while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WLDR)
 		;
-/* Sequence to enable the watchdog */
+	/* Sequence to enable the watchdog */
 	writel(0xBBBB, &priv->regs->wdtwspr);
 	while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WSPR)
 		;
@@ -219,6 +219,16 @@ static int omap3_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
 	while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WSPR)
 		;
 
+	/* Trigger the watchdog to actually reload the counter. */
+	while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WTGR)
+		;
+
+	priv->wdt_trgr_pattern = ~(priv->wdt_trgr_pattern);
+	writel(priv->wdt_trgr_pattern, &priv->regs->wdtwtgr);
+
+	while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WTGR)
+		;
+
 	return 0;
 }