Merge tag 'xilinx-for-v2021.07-rc2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2021.07-rc2

xilinx:
- Enable saving variables based on bootmode
- Cleanup usb dfu setup and wire it up with usb bootmode
- Fix bootscript address logic
- Remove GD references (spi, Versal)
- Enable capsule update

clk:
- Small Kconfig fix

net:
- Fix gmii2rgmii bridge binding

usb:
- Propagate error (dfu gadget)

3 files changed, 3 insertions, 6 deletions

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4aeaa0cd58..40a5a5dd88 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -125,7 +125,7 @@ config CLK_ZYNQ
 	depends on CLK && ARCH_ZYNQ
 	default y
 	help
-	  This clock driver adds support for clock realted settings for
+	  This clock driver adds support for clock related settings for
 	  Zynq platform.
 
 config CLK_ZYNQMP
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index dcdef9e661..ed197fa46d 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -948,9 +948,9 @@ static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
 						 phy_interface_t interface)
 {
 	struct phy_device *phydev = NULL;
-	ofnode node = dev_ofnode(dev);
+	ofnode node;
 
-	while (ofnode_valid(node)) {
+	ofnode_for_each_subnode(node, dev_ofnode(dev)) {
 		node = ofnode_by_compatible(node, "xlnx,gmii-to-rgmii-1.0");
 		if (ofnode_valid(node)) {
 			phydev = phy_device_create(bus, 0,
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index f8d13d193e..17780066ae 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -10,7 +10,6 @@
 #include <log.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/cache.h>
-#include <asm/global_data.h>
 #include <asm/io.h>
 #include <clk.h>
 #include <dm.h>
@@ -156,8 +155,6 @@ struct zynqmp_qspi_dma_regs {
 	u32 dmadstmsb;	/* 0x28 */
 };
 
-DECLARE_GLOBAL_DATA_PTR;
-
 struct zynqmp_qspi_plat {
 	struct zynqmp_qspi_regs *regs;
 	struct zynqmp_qspi_dma_regs *dma_regs;