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authorMarek BehĂșn <marek.behun@nic.cz>2019-08-07 16:01:56 +0300
committerStefan Roese <sr@denx.de>2019-08-12 14:59:31 +0300
commit193a1e9f196b7fb7e913a70936c8a49060a1859c (patch)
tree1dbaaee4259272ba2b244c07320c8c91ac6c6552 /drivers
parent6de5a717c7a19cedbb2867a39af1daca06f3b434 (diff)
downloadu-boot-193a1e9f196b7fb7e913a70936c8a49060a1859c.tar.xz
pci: pci_mvebu: set BAR0 after memory space is set
The non-DM version of this driver used to set BAR0 register after the calls to pci_set_region. I found out that for some strange reason the ath10k driver in kernel fails to work if this is done the other way around. I know that Linux's driver should not depend on how U-Boot does things, but for some strange reason it does and this seems to be the simplest solution. Fix it since it caused regressions on Omnia. Signed-off-by: Marek BehĂșn <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: VlaoMao <vlaomao@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pci/pci_mvebu.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index e21dc10c2f..f9b08f38a1 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -313,10 +313,6 @@ static int mvebu_pcie_probe(struct udevice *dev)
reg |= BIT(10); /* disable interrupts */
writel(reg, pcie->base + PCIE_CMD_OFF);
- /* Set BAR0 to internal registers */
- writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
- writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
-
/* PCI memory space */
pci_set_region(hose->regions + 0, pcie->mem.start,
pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
@@ -326,6 +322,10 @@ static int mvebu_pcie_probe(struct udevice *dev)
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 2;
+ /* Set BAR0 to internal registers */
+ writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
+ writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
+
bus++;
return 0;