Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi

This contains some fixes, and the first bunch of some clean up patches
to get rid of legacy GPIO and PMIC code.
Highlight is the DM AXP PMIC driver, which is required to convert some
drivers over to use DM regulators, and also is required to get rid
of some less optimal PMIC setup code in Trusted Firmware. This isn't
enabled by any defconfig yet, but can be enabled manually and works. For
the full glory some patches are still missing, and this requires more
testing, which would be simpler if the core code is upstream.

13 files changed, 591 insertions, 122 deletions

diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 8c81b1ac45..136ba89293 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -16,6 +16,7 @@
 static const struct ccu_clk_gate a64_gates[] = {
 	[CLK_PLL_PERIPH0]	= GATE(0x028, BIT(31)),
 
+	[CLK_BUS_MIPI_DSI]	= GATE(0x060, BIT(1)),
 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
@@ -28,6 +29,11 @@ static const struct ccu_clk_gate a64_gates[] = {
 	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(28)),
 	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(29)),
 
+	[CLK_BUS_TCON0]		= GATE(0x064, BIT(3)),
+	[CLK_BUS_TCON1]		= GATE(0x064, BIT(4)),
+	[CLK_BUS_HDMI]		= GATE(0x064, BIT(11)),
+	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
+
 	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
 
 	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
@@ -48,6 +54,15 @@ static const struct ccu_clk_gate a64_gates[] = {
 	[CLK_USB_HSIC_12M]	= GATE(0x0cc, BIT(11)),
 	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
 	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
+
+	[CLK_DE]		= GATE(0x104, BIT(31)),
+	[CLK_TCON0]		= GATE(0x118, BIT(31)),
+	[CLK_TCON1]		= GATE(0x11c, BIT(31)),
+
+	[CLK_HDMI]		= GATE(0x150, BIT(31)),
+	[CLK_HDMI_DDC]		= GATE(0x154, BIT(31)),
+
+	[CLK_DSI_DPHY]		= GATE(0x168, BIT(15)),
 };
 
 static const struct ccu_reset a64_resets[] = {
@@ -55,6 +70,7 @@ static const struct ccu_reset a64_resets[] = {
 	[RST_USB_PHY1]          = RESET(0x0cc, BIT(1)),
 	[RST_USB_HSIC]          = RESET(0x0cc, BIT(2)),
 
+	[RST_BUS_MIPI_DSI]	= RESET(0x2c0, BIT(1)),
 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
@@ -67,6 +83,12 @@ static const struct ccu_reset a64_resets[] = {
 	[RST_BUS_OHCI0]         = RESET(0x2c0, BIT(28)),
 	[RST_BUS_OHCI1]         = RESET(0x2c0, BIT(29)),
 
+	[RST_BUS_TCON0]		= RESET(0x2c4, BIT(3)),
+	[RST_BUS_TCON1]		= RESET(0x2c4, BIT(4)),
+	[RST_BUS_HDMI0]		= RESET(0x2c4, BIT(10)),
+	[RST_BUS_HDMI1]		= RESET(0x2c4, BIT(11)),
+	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
+
 	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
 	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
 	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 3562da61d1..d5af37b3d7 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -14,6 +14,7 @@
 #include <linux/bitops.h>
 
 static struct ccu_clk_gate a83t_gates[] = {
+	[CLK_BUS_MIPI_DSI]	= GATE(0x060, BIT(1)),
 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
@@ -25,6 +26,11 @@ static struct ccu_clk_gate a83t_gates[] = {
 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(27)),
 	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(29)),
 
+	[CLK_BUS_TCON0]		= GATE(0x064, BIT(4)),
+	[CLK_BUS_TCON1]		= GATE(0x064, BIT(5)),
+	[CLK_BUS_HDMI]		= GATE(0x064, BIT(11)),
+	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
+
 	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
 
 	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
@@ -44,6 +50,15 @@ static struct ccu_clk_gate a83t_gates[] = {
 	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),
 	[CLK_USB_HSIC_12M]	= GATE(0x0cc, BIT(11)),
 	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
+
+	[CLK_TCON0]		= GATE(0x118, BIT(31)),
+	[CLK_TCON1]		= GATE(0x11c, BIT(31)),
+
+	[CLK_HDMI]		= GATE(0x150, BIT(31)),
+	[CLK_HDMI_SLOW]		= GATE(0x154, BIT(31)),
+
+	[CLK_MIPI_DSI0]		= GATE(0x168, BIT(31)),
+	[CLK_MIPI_DSI1]		= GATE(0x16c, BIT(31)),
 };
 
 static struct ccu_reset a83t_resets[] = {
@@ -51,6 +66,7 @@ static struct ccu_reset a83t_resets[] = {
 	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
 	[RST_USB_HSIC]		= RESET(0x0cc, BIT(2)),
 
+	[RST_BUS_MIPI_DSI]	= RESET(0x2c0, BIT(1)),
 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
@@ -62,6 +78,12 @@ static struct ccu_reset a83t_resets[] = {
 	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(27)),
 	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(29)),
 
+	[RST_BUS_TCON0]		= RESET(0x2c4, BIT(4)),
+	[RST_BUS_TCON1]		= RESET(0x2c4, BIT(5)),
+	[RST_BUS_HDMI0]		= RESET(0x2c4, BIT(10)),
+	[RST_BUS_HDMI1]		= RESET(0x2c4, BIT(11)),
+	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
+
 	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
 	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
 	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 17ab3b5c27..213ab510ed 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -32,6 +32,11 @@ static struct ccu_clk_gate h3_gates[] = {
 	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(30)),
 	[CLK_BUS_OHCI3]		= GATE(0x060, BIT(31)),
 
+	[CLK_BUS_TCON0]		= GATE(0x064, BIT(3)),
+	[CLK_BUS_TCON1]		= GATE(0x064, BIT(4)),
+	[CLK_BUS_HDMI]		= GATE(0x064, BIT(11)),
+	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
+
 	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
 
 	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
@@ -55,6 +60,12 @@ static struct ccu_clk_gate h3_gates[] = {
 	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
 	[CLK_USB_OHCI2]		= GATE(0x0cc, BIT(18)),
 	[CLK_USB_OHCI3]		= GATE(0x0cc, BIT(19)),
+
+	[CLK_DE]		= GATE(0x104, BIT(31)),
+	[CLK_TCON0]		= GATE(0x118, BIT(31)),
+
+	[CLK_HDMI]		= GATE(0x150, BIT(31)),
+	[CLK_HDMI_DDC]		= GATE(0x154, BIT(31)),
 };
 
 static struct ccu_reset h3_resets[] = {
@@ -79,6 +90,12 @@ static struct ccu_reset h3_resets[] = {
 	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(30)),
 	[RST_BUS_OHCI3]		= RESET(0x2c0, BIT(31)),
 
+	[RST_BUS_TCON0]		= RESET(0x2c4, BIT(3)),
+	[RST_BUS_TCON1]		= RESET(0x2c4, BIT(4)),
+	[RST_BUS_HDMI0]		= RESET(0x2c4, BIT(10)),
+	[RST_BUS_HDMI1]		= RESET(0x2c4, BIT(11)),
+	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
+
 	[RST_BUS_EPHY]		= RESET(0x2c8, BIT(2)),
 
 	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index 041bc5e80e..24eb9725db 100644
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -18,6 +18,9 @@ static struct ccu_clk_gate h6_gates[] = {
 
 	[CLK_APB1]		= GATE_DUMMY,
 
+	[CLK_DE]		= GATE(0x600, BIT(31)),
+	[CLK_BUS_DE]		= GATE(0x60c, BIT(0)),
+
 	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
 	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
 	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
@@ -55,9 +58,21 @@ static struct ccu_clk_gate h6_gates[] = {
 	[CLK_BUS_XHCI]		= GATE(0xa8c, BIT(5)),
 	[CLK_BUS_EHCI3]		= GATE(0xa8c, BIT(7)),
 	[CLK_BUS_OTG]		= GATE(0xa8c, BIT(8)),
+
+	[CLK_HDMI]		= GATE(0xb00, BIT(31)),
+	[CLK_HDMI_SLOW]		= GATE(0xb04, BIT(31)),
+	[CLK_HDMI_CEC]		= GATE(0xb10, BIT(31)),
+	[CLK_BUS_HDMI]		= GATE(0xb1c, BIT(0)),
+	[CLK_BUS_TCON_TOP]	= GATE(0xb5c, BIT(0)),
+	[CLK_TCON_LCD0]		= GATE(0xb60, BIT(31)),
+	[CLK_BUS_TCON_LCD0]	= GATE(0xb7c, BIT(0)),
+	[CLK_TCON_TV0]		= GATE(0xb80, BIT(31)),
+	[CLK_BUS_TCON_TV0]	= GATE(0xb9c, BIT(0)),
 };
 
 static struct ccu_reset h6_resets[] = {
+	[RST_BUS_DE]		= RESET(0x60c, BIT(16)),
+
 	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
 	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
 	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
@@ -89,6 +104,12 @@ static struct ccu_reset h6_resets[] = {
 	[RST_BUS_XHCI]		= RESET(0xa8c, BIT(21)),
 	[RST_BUS_EHCI3]		= RESET(0xa8c, BIT(23)),
 	[RST_BUS_OTG]		= RESET(0xa8c, BIT(24)),
+
+	[RST_BUS_HDMI]		= RESET(0xb1c, BIT(16)),
+	[RST_BUS_HDMI_SUB]	= RESET(0xb1c, BIT(17)),
+	[RST_BUS_TCON_TOP]	= RESET(0xb5c, BIT(16)),
+	[RST_BUS_TCON_LCD0]	= RESET(0xb7c, BIT(16)),
+	[RST_BUS_TCON_TV0]	= RESET(0xb9c, BIT(16)),
 };
 
 const struct ccu_desc h6_ccu_desc = {
diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
index 964636d728..88d6bf3420 100644
--- a/drivers/clk/sunxi/clk_h616.c
+++ b/drivers/clk/sunxi/clk_h616.c
@@ -17,6 +17,9 @@ static struct ccu_clk_gate h616_gates[] = {
 
 	[CLK_APB1]		= GATE_DUMMY,
 
+	[CLK_DE]		= GATE(0x600, BIT(31)),
+	[CLK_BUS_DE]		= GATE(0x60c, BIT(0)),
+
 	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
 	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
 	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
@@ -64,9 +67,21 @@ static struct ccu_clk_gate h616_gates[] = {
 	[CLK_BUS_EHCI2]		= GATE(0xa8c, BIT(6)),
 	[CLK_BUS_EHCI3]		= GATE(0xa8c, BIT(7)),
 	[CLK_BUS_OTG]		= GATE(0xa8c, BIT(8)),
+
+	[CLK_HDMI]		= GATE(0xb00, BIT(31)),
+	[CLK_HDMI_SLOW]		= GATE(0xb04, BIT(31)),
+	[CLK_HDMI_CEC]		= GATE(0xb10, BIT(31)),
+	[CLK_BUS_HDMI]		= GATE(0xb1c, BIT(0)),
+	[CLK_BUS_TCON_TOP]	= GATE(0xb5c, BIT(0)),
+	[CLK_TCON_TV0]		= GATE(0xb80, BIT(31)),
+	[CLK_TCON_TV1]		= GATE(0xb84, BIT(31)),
+	[CLK_BUS_TCON_TV0]	= GATE(0xb9c, BIT(0)),
+	[CLK_BUS_TCON_TV1]	= GATE(0xb9c, BIT(1)),
 };
 
 static struct ccu_reset h616_resets[] = {
+	[RST_BUS_DE]		= RESET(0x60c, BIT(16)),
+
 	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
 	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
 	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
@@ -107,6 +122,12 @@ static struct ccu_reset h616_resets[] = {
 	[RST_BUS_EHCI2]		= RESET(0xa8c, BIT(22)),
 	[RST_BUS_EHCI3]		= RESET(0xa8c, BIT(23)),
 	[RST_BUS_OTG]		= RESET(0xa8c, BIT(24)),
+
+	[RST_BUS_HDMI]		= RESET(0xb1c, BIT(16)),
+	[RST_BUS_HDMI_SUB]	= RESET(0xb1c, BIT(17)),
+	[RST_BUS_TCON_TOP]	= RESET(0xb5c, BIT(16)),
+	[RST_BUS_TCON_TV0]	= RESET(0xb9c, BIT(16)),
+	[RST_BUS_TCON_TV1]	= RESET(0xb9c, BIT(17)),
 };
 
 const struct ccu_desc h616_ccu_desc = {
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index ef743d65b7..630e80d2b4 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -14,6 +14,7 @@
 #include <linux/bitops.h>
 
 static struct ccu_clk_gate r40_gates[] = {
+	[CLK_BUS_MIPI_DSI]	= GATE(0x060, BIT(1)),
 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
@@ -30,7 +31,15 @@ static struct ccu_clk_gate r40_gates[] = {
 	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(30)),
 	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(31)),
 
+	[CLK_BUS_HDMI0]		= GATE(0x064, BIT(10)),
+	[CLK_BUS_HDMI1]		= GATE(0x064, BIT(11)),
+	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
 	[CLK_BUS_GMAC]		= GATE(0x064, BIT(17)),
+	[CLK_BUS_TCON_LCD0]	= GATE(0x064, BIT(26)),
+	[CLK_BUS_TCON_LCD1]	= GATE(0x064, BIT(27)),
+	[CLK_BUS_TCON_TV0]	= GATE(0x064, BIT(28)),
+	[CLK_BUS_TCON_TV1]	= GATE(0x064, BIT(29)),
+	[CLK_BUS_TCON_TOP]	= GATE(0x064, BIT(30)),
 
 	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
 
@@ -59,6 +68,17 @@ static struct ccu_clk_gate r40_gates[] = {
 	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
 	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
 	[CLK_USB_OHCI2]		= GATE(0x0cc, BIT(18)),
+
+	[CLK_DE]		= GATE(0x104, BIT(31)),
+	[CLK_TCON_LCD0]		= GATE(0x110, BIT(31)),
+	[CLK_TCON_LCD1]		= GATE(0x114, BIT(31)),
+	[CLK_TCON_TV0]		= GATE(0x118, BIT(31)),
+	[CLK_TCON_TV1]		= GATE(0x11c, BIT(31)),
+
+	[CLK_HDMI]		= GATE(0x150, BIT(31)),
+	[CLK_HDMI_SLOW]		= GATE(0x154, BIT(31)),
+
+	[CLK_DSI_DPHY]		= GATE(0x168, BIT(15)),
 };
 
 static struct ccu_reset r40_resets[] = {
@@ -66,6 +86,7 @@ static struct ccu_reset r40_resets[] = {
 	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
 	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
 
+	[RST_BUS_MIPI_DSI]	= RESET(0x2c0, BIT(1)),
 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
@@ -82,7 +103,15 @@ static struct ccu_reset r40_resets[] = {
 	[RST_BUS_OHCI1]		= RESET(0x2c0, BIT(30)),
 	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(31)),
 
+	[RST_BUS_HDMI0]		= RESET(0x2c4, BIT(10)),
+	[RST_BUS_HDMI1]		= RESET(0x2c4, BIT(11)),
+	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
 	[RST_BUS_GMAC]		= RESET(0x2c4, BIT(17)),
+	[RST_BUS_TCON_LCD0]	= RESET(0x2c4, BIT(26)),
+	[RST_BUS_TCON_LCD1]	= RESET(0x2c4, BIT(27)),
+	[RST_BUS_TCON_TV0]	= RESET(0x2c4, BIT(28)),
+	[RST_BUS_TCON_TV1]	= RESET(0x2c4, BIT(29)),
+	[RST_BUS_TCON_TOP]	= RESET(0x2c4, BIT(30)),
 
 	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
 	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index f2fd11eac2..6524c13540 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -20,6 +20,9 @@ static struct ccu_clk_gate v3s_gates[] = {
 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
 
+	[CLK_BUS_TCON0]		= GATE(0x064, BIT(4)),
+	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
+
 	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
 
 	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
@@ -31,6 +34,9 @@ static struct ccu_clk_gate v3s_gates[] = {
 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
 
 	[CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
+
+	[CLK_DE]		= GATE(0x104, BIT(31)),
+	[CLK_TCON0]		= GATE(0x118, BIT(31)),
 };
 
 static struct ccu_reset v3s_resets[] = {
@@ -42,6 +48,9 @@ static struct ccu_reset v3s_resets[] = {
 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
 
+	[RST_BUS_TCON0]		= RESET(0x2c4, BIT(4)),
+	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
+
 	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
 	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
 	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 1bb7b6d0e9..23bc7da917 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -5,6 +5,12 @@
  * Aaron <leafy.myeh@allwinnertech.com>
  *
  * MMC driver for allwinner sunxi platform.
+ *
+ * This driver is used by the (ARM) SPL with the legacy MMC interface, and
+ * by U-Boot proper using the full DM interface. The actual hardware access
+ * code is common, and comes first in this file.
+ * The legacy MMC interface implementation comes next, followed by the
+ * proper DM_MMC implementation at the end.
  */
 
 #include <common.h>
@@ -40,69 +46,6 @@ struct sunxi_mmc_priv {
 	struct mmc_config cfg;
 };
 
-#if !CONFIG_IS_ENABLED(DM_MMC)
-/* support 4 mmc hosts */
-struct sunxi_mmc_priv mmc_host[4];
-
-static int sunxi_mmc_getcd_gpio(int sdc_no)
-{
-	switch (sdc_no) {
-	case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
-	case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
-	case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
-	case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
-	}
-	return -EINVAL;
-}
-
-static int mmc_resource_init(int sdc_no)
-{
-	struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
-	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-	int cd_pin, ret = 0;
-
-	debug("init mmc %d resource\n", sdc_no);
-
-	switch (sdc_no) {
-	case 0:
-		priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
-		priv->mclkreg = &ccm->sd0_clk_cfg;
-		break;
-	case 1:
-		priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
-		priv->mclkreg = &ccm->sd1_clk_cfg;
-		break;
-#ifdef SUNXI_MMC2_BASE
-	case 2:
-		priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
-		priv->mclkreg = &ccm->sd2_clk_cfg;
-		break;
-#endif
-#ifdef SUNXI_MMC3_BASE
-	case 3:
-		priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
-		priv->mclkreg = &ccm->sd3_clk_cfg;
-		break;
-#endif
-	default:
-		printf("Wrong mmc number %d\n", sdc_no);
-		return -1;
-	}
-	priv->mmc_no = sdc_no;
-
-	cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
-	if (cd_pin >= 0) {
-		ret = gpio_request(cd_pin, "mmc_cd");
-		if (!ret) {
-			sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
-			ret = gpio_direction_input(cd_pin);
-		}
-	}
-
-	return ret;
-}
-#endif
-
 /*
  * All A64 and later MMC controllers feature auto-calibration. This would
  * normally be detected via the compatible string, but we need something
@@ -290,19 +233,6 @@ static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
 	return 0;
 }
 
-#if !CONFIG_IS_ENABLED(DM_MMC)
-static int sunxi_mmc_core_init(struct mmc *mmc)
-{
-	struct sunxi_mmc_priv *priv = mmc->priv;
-
-	/* Reset controller */
-	writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
-	udelay(1000);
-
-	return 0;
-}
-#endif
-
 static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
 				 struct mmc_data *data)
 {
@@ -507,39 +437,80 @@ out:
 	return error;
 }
 
+/* non-DM code here is used by the (ARM) SPL only */
+
 #if !CONFIG_IS_ENABLED(DM_MMC)
-static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
+/* support 4 mmc hosts */
+struct sunxi_mmc_priv mmc_host[4];
+
+static int mmc_resource_init(int sdc_no)
 {
-	struct sunxi_mmc_priv *priv = mmc->priv;
+	struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
+	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
-	return sunxi_mmc_set_ios_common(priv, mmc);
+	debug("init mmc %d resource\n", sdc_no);
+
+	switch (sdc_no) {
+	case 0:
+		priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
+		priv->mclkreg = &ccm->sd0_clk_cfg;
+		break;
+	case 1:
+		priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
+		priv->mclkreg = &ccm->sd1_clk_cfg;
+		break;
+#ifdef SUNXI_MMC2_BASE
+	case 2:
+		priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
+		priv->mclkreg = &ccm->sd2_clk_cfg;
+		break;
+#endif
+#ifdef SUNXI_MMC3_BASE
+	case 3:
+		priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
+		priv->mclkreg = &ccm->sd3_clk_cfg;
+		break;
+#endif
+	default:
+		printf("Wrong mmc number %d\n", sdc_no);
+		return -1;
+	}
+	priv->mmc_no = sdc_no;
+
+	return 0;
 }
 
-static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
-				     struct mmc_data *data)
+static int sunxi_mmc_core_init(struct mmc *mmc)
 {
 	struct sunxi_mmc_priv *priv = mmc->priv;
 
-	return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
+	/* Reset controller */
+	writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
+	udelay(1000);
+
+	return 0;
 }
 
-static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
+static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
 {
 	struct sunxi_mmc_priv *priv = mmc->priv;
-	int cd_pin;
 
-	cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
-	if (cd_pin < 0)
-		return 1;
+	return sunxi_mmc_set_ios_common(priv, mmc);
+}
 
-	return !gpio_get_value(cd_pin);
+static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
+				     struct mmc_data *data)
+{
+	struct sunxi_mmc_priv *priv = mmc->priv;
+
+	return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
 }
 
+/* .getcd is not needed by the SPL */
 static const struct mmc_ops sunxi_mmc_ops = {
 	.send_cmd	= sunxi_mmc_send_cmd_legacy,
 	.set_ios	= sunxi_mmc_set_ios_legacy,
 	.init		= sunxi_mmc_core_init,
-	.getcd		= sunxi_mmc_getcd_legacy,
 };
 
 struct mmc *sunxi_mmc_init(int sdc_no)
@@ -595,7 +566,8 @@ struct mmc *sunxi_mmc_init(int sdc_no)
 
 	return mmc_create(cfg, priv);
 }
-#else
+
+#else /* CONFIG_DM_MMC code below, as used by U-Boot proper */
 
 static int sunxi_mmc_set_ios(struct udevice *dev)
 {
diff --git a/drivers/power/pmic/axp.c b/drivers/power/pmic/axp.c
index 0f2b24a8b5..025dac24f2 100644
--- a/drivers/power/pmic/axp.c
+++ b/drivers/power/pmic/axp.c
@@ -45,14 +45,32 @@ static struct dm_pmic_ops axp_pmic_ops = {
 	.write		= dm_i2c_write,
 };
 
+static const struct pmic_child_info axp_pmic_child_info[] = {
+	{ "aldo",	"axp_regulator" },
+	{ "bldo",	"axp_regulator" },
+	{ "cldo",	"axp_regulator" },
+	{ "dc",		"axp_regulator" },
+	{ "dldo",	"axp_regulator" },
+	{ "eldo",	"axp_regulator" },
+	{ "fldo",	"axp_regulator" },
+	{ "ldo",	"axp_regulator" },
+	{ "sw",		"axp_regulator" },
+	{ }
+};
+
 static int axp_pmic_bind(struct udevice *dev)
 {
+	ofnode regulators_node;
 	int ret;
 
 	ret = dm_scan_fdt_dev(dev);
 	if (ret)
 		return ret;
 
+	regulators_node = dev_read_subnode(dev, "regulators");
+	if (ofnode_valid(regulators_node))
+		pmic_bind_children(dev, regulators_node, axp_pmic_child_info);
+
 	if (CONFIG_IS_ENABLED(SYSRESET)) {
 		ret = device_bind_driver_to_node(dev, "axp_sysreset", "axp_sysreset",
 						 dev_ofnode(dev), NULL);
@@ -64,15 +82,15 @@ static int axp_pmic_bind(struct udevice *dev)
 }
 
 static const struct udevice_id axp_pmic_ids[] = {
-	{ .compatible = "x-powers,axp152" },
-	{ .compatible = "x-powers,axp202" },
-	{ .compatible = "x-powers,axp209" },
-	{ .compatible = "x-powers,axp221" },
-	{ .compatible = "x-powers,axp223" },
-	{ .compatible = "x-powers,axp803" },
-	{ .compatible = "x-powers,axp806" },
-	{ .compatible = "x-powers,axp809" },
-	{ .compatible = "x-powers,axp813" },
+	{ .compatible = "x-powers,axp152", .data = AXP152_ID },
+	{ .compatible = "x-powers,axp202", .data = AXP202_ID },
+	{ .compatible = "x-powers,axp209", .data = AXP209_ID },
+	{ .compatible = "x-powers,axp221", .data = AXP221_ID },
+	{ .compatible = "x-powers,axp223", .data = AXP223_ID },
+	{ .compatible = "x-powers,axp803", .data = AXP803_ID },
+	{ .compatible = "x-powers,axp806", .data = AXP806_ID },
+	{ .compatible = "x-powers,axp809", .data = AXP809_ID },
+	{ .compatible = "x-powers,axp813", .data = AXP813_ID },
 	{ }
 };
 
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index c02e6377d8..c346d03507 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -43,6 +43,20 @@ config REGULATOR_AS3722
 	  but does not yet support change voltages. Currently this must be
 	  done using direct register writes to the PMIC.
 
+config REGULATOR_AXP
+	bool "Enable driver for X-Powers AXP PMIC regulators"
+	depends on DM_REGULATOR && PMIC_AXP
+	help
+	  Enable support for the regulators (DCDCs, LDOs) in the
+	  X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
+
+config SPL_REGULATOR_AXP
+	bool "Enable driver for X-Powers AXP PMIC regulators in SPL"
+	depends on SPL_DM_REGULATOR && SPL_PMIC_AXP
+	help
+	  Enable support in SPL for the regulators (DCDCs, LDOs) in the
+	  X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
+
 config DM_REGULATOR_BD71837
 	bool "Enable Driver Model for ROHM BD71837/BD71847 regulators"
 	depends on DM_REGULATOR && DM_PMIC_BD71837
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 68e4c0f9dd..2d97e1033a 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -7,6 +7,7 @@
 obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
 obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
 obj-$(CONFIG_REGULATOR_AS3722)	+= as3722_regulator.o
+obj-$(CONFIG_$(SPL_)REGULATOR_AXP) += axp_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_DA9063) += da9063.o
 obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
 obj-$(CONFIG_DM_REGULATOR_NPCM8XX) += npcm8xx_regulator.o
diff --git a/drivers/power/regulator/axp_regulator.c b/drivers/power/regulator/axp_regulator.c
new file mode 100644
index 0000000000..02f320eac1
--- /dev/null
+++ b/drivers/power/regulator/axp_regulator.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023 Samuel Holland <samuel@sholland.org>
+ */
+
+#include <axp_pmic.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/device-internal.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+
+#define NA 0xff
+
+struct axp_regulator_plat {
+	const char	*name;
+	u8		enable_reg;
+	u8		enable_mask;
+	u8		volt_reg;
+	u8		volt_mask;
+	u16		min_mV;
+	u16		max_mV;
+	u8		step_mV;
+	u8		split;
+	const u16	*table;
+};
+
+static int axp_regulator_get_value(struct udevice *dev)
+{
+	const struct axp_regulator_plat *plat = dev_get_plat(dev);
+	int mV, sel;
+
+	if (plat->volt_reg == NA)
+		return -EINVAL;
+
+	sel = pmic_reg_read(dev->parent, plat->volt_reg);
+	if (sel < 0)
+		return sel;
+
+	sel &= plat->volt_mask;
+	sel >>= ffs(plat->volt_mask) - 1;
+
+	if (plat->table) {
+		mV = plat->table[sel];
+	} else {
+		if (sel > plat->split)
+			sel = plat->split + (sel - plat->split) * 2;
+		mV = plat->min_mV + sel * plat->step_mV;
+	}
+
+	return mV * 1000;
+}
+
+static int axp_regulator_set_value(struct udevice *dev, int uV)
+{
+	const struct axp_regulator_plat *plat = dev_get_plat(dev);
+	int mV = uV / 1000;
+	uint sel, shift;
+
+	if (plat->volt_reg == NA)
+		return -EINVAL;
+	if (mV < plat->min_mV || mV > plat->max_mV)
+		return -EINVAL;
+
+	shift = ffs(plat->volt_mask) - 1;
+
+	if (plat->table) {
+		/*
+		 * The table must be monotonically increasing and
+		 * have an entry for each possible field value.
+		 */
+		sel = plat->volt_mask >> shift;
+		while (sel && plat->table[sel] > mV)
+			sel--;
+	} else {
+		sel = (mV - plat->min_mV) / plat->step_mV;
+		if (sel > plat->split)
+			sel = plat->split + (sel - plat->split) / 2;
+	}
+
+	return pmic_clrsetbits(dev->parent, plat->volt_reg,
+			       plat->volt_mask, sel << shift);
+}
+
+static int axp_regulator_get_enable(struct udevice *dev)
+{
+	const struct axp_regulator_plat *plat = dev_get_plat(dev);
+	int reg;
+
+	reg = pmic_reg_read(dev->parent, plat->enable_reg);
+	if (reg < 0)
+		return reg;
+
+	return (reg & plat->enable_mask) == plat->enable_mask;
+}
+
+static int axp_regulator_set_enable(struct udevice *dev, bool enable)
+{
+	const struct axp_regulator_plat *plat = dev_get_plat(dev);
+
+	return pmic_clrsetbits(dev->parent, plat->enable_reg,
+			       plat->enable_mask,
+			       enable ? plat->enable_mask : 0);
+}
+
+static const struct dm_regulator_ops axp_regulator_ops = {
+	.get_value		= axp_regulator_get_value,
+	.set_value		= axp_regulator_set_value,
+	.get_enable		= axp_regulator_get_enable,
+	.set_enable		= axp_regulator_set_enable,
+};
+
+static const u16 axp152_dcdc1_table[] = {
+	1700, 1800, 1900, 2000, 2100, 2400, 2500, 2600,
+	2700, 2800, 3000, 3100, 3200, 3300, 3400, 3500,
+};
+
+static const u16 axp152_aldo12_table[] = {
+	1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900,
+	2000, 2500, 2700, 2800, 3000, 3100, 3200, 3300,
+};
+
+static const u16 axp152_ldo0_table[] = {
+	5000, 3300, 2800, 2500,
+};
+
+static const struct axp_regulator_plat axp152_regulators[] = {
+	{ "dcdc1", 0x12, BIT(7), 0x26, 0x0f, .table = axp152_dcdc1_table },
+	{ "dcdc2", 0x12, BIT(6), 0x23, 0x3f,  700, 2275,  25, NA },
+	{ "dcdc3", 0x12, BIT(5), 0x27, 0x3f,  700, 3500,  50, NA },
+	{ "dcdc4", 0x12, BIT(4), 0x2b, 0x7f,  700, 3500,  25, NA },
+	{ "aldo1", 0x12, BIT(3), 0x28, 0xf0, .table = axp152_aldo12_table },
+	{ "aldo2", 0x12, BIT(2), 0x28, 0x0f, .table = axp152_aldo12_table },
+	{ "dldo1", 0x12, BIT(1), 0x29, 0x1f,  700, 3500, 100, NA },
+	{ "dldo2", 0x12, BIT(0), 0x2a, 0x1f,  700, 3500, 100, NA },
+	{ "ldo0",  0x15, BIT(7), 0x15, 0x30, .table = axp152_ldo0_table },
+	{ }
+};
+
+static const u16 axp20x_ldo4_table[] = {
+	1250, 1300, 1400, 1500, 1600, 1700, 1800, 1900,
+	2000, 2500, 2700, 2800, 3000, 3100, 3200, 3300,
+};
+
+static const struct axp_regulator_plat axp20x_regulators[] = {
+	{ "dcdc2", 0x12, BIT(4), 0x23, 0x3f,  700, 2275,  25, NA },
+	{ "dcdc3", 0x12, BIT(1), 0x27, 0x7f,  700, 3500,  25, NA },
+	{ "ldo2",  0x12, BIT(2), 0x28, 0xf0, 1800, 3300, 100, NA },
+	{ "ldo3",  0x12, BIT(6), 0x29, 0x7f,  700, 2275,  25, NA },
+	{ "ldo4",  0x12, BIT(3), 0x28, 0x0f, .table = axp20x_ldo4_table },
+	{ }
+};
+
+static const struct axp_regulator_plat axp22x_regulators[] = {
+	{"dc5ldo", 0x10, BIT(0), 0x1c, 0x07,  700, 1400, 100, NA },
+	{ "dcdc1", 0x10, BIT(1), 0x21, 0x1f, 1600, 3400, 100, NA },
+	{ "dcdc2", 0x10, BIT(2), 0x22, 0x3f,  600, 1540,  20, NA },
+	{ "dcdc3", 0x10, BIT(3), 0x23, 0x3f,  600, 1860,  20, NA },
+	{ "dcdc4", 0x10, BIT(4), 0x24, 0x3f,  600, 1540,  20, NA },
+	{ "dcdc5", 0x10, BIT(5), 0x25, 0x1f, 1000, 2550,  50, NA },
+	{ "aldo1", 0x10, BIT(6), 0x28, 0x1f,  700, 3300, 100, NA },
+	{ "aldo2", 0x10, BIT(7), 0x29, 0x1f,  700, 3300, 100, NA },
+	{ "aldo3", 0x13, BIT(7), 0x2a, 0x1f,  700, 3300, 100, NA },
+	{ "dldo1", 0x12, BIT(3), 0x15, 0x1f,  700, 3300, 100, NA },
+	{ "dldo2", 0x12, BIT(4), 0x16, 0x1f,  700, 3300, 100, NA },
+	{ "dldo3", 0x12, BIT(5), 0x17, 0x1f,  700, 3300, 100, NA },
+	{ "dldo4", 0x12, BIT(6), 0x18, 0x1f,  700, 3300, 100, NA },
+	{ "eldo1", 0x12, BIT(0), 0x19, 0x1f,  700, 3300, 100, NA },
+	{ "eldo2", 0x12, BIT(1), 0x1a, 0x1f,  700, 3300, 100, NA },
+	{ "eldo3", 0x12, BIT(2), 0x1b, 0x1f,  700, 3300, 100, NA },
+	{ "dc1sw", 0x12, BIT(7),   NA,   NA,   NA,   NA,  NA, NA },
+	{ }
+};
+
+static const struct axp_regulator_plat axp803_regulators[] = {
+	{ "dcdc1", 0x10, BIT(0), 0x20, 0x1f, 1600, 3400, 100, NA },
+	{ "dcdc2", 0x10, BIT(1), 0x21, 0x7f,  500, 1300,  10, 70 },
+	{ "dcdc3", 0x10, BIT(2), 0x22, 0x7f,  500, 1300,  10, 70 },
+	{ "dcdc4", 0x10, BIT(3), 0x23, 0x7f,  500, 1300,  10, 70 },
+	{ "dcdc5", 0x10, BIT(4), 0x24, 0x7f,  800, 1840,  10, 32 },
+	{ "dcdc6", 0x10, BIT(5), 0x25, 0x7f,  600, 1520,  10, 50 },
+	{ "aldo1", 0x13, BIT(5), 0x28, 0x1f,  700, 3300, 100, NA },
+	{ "aldo2", 0x13, BIT(6), 0x29, 0x1f,  700, 3300, 100, NA },
+	{ "aldo3", 0x13, BIT(7), 0x2a, 0x1f,  700, 3300, 100, NA },
+	{ "dldo1", 0x12, BIT(3), 0x15, 0x1f,  700, 3300, 100, NA },
+	{ "dldo2", 0x12, BIT(4), 0x16, 0x1f,  700, 4200, 100, 27 },
+	{ "dldo3", 0x12, BIT(5), 0x17, 0x1f,  700, 3300, 100, NA },
+	{ "dldo4", 0x12, BIT(6), 0x18, 0x1f,  700, 3300, 100, NA },
+	{ "eldo1", 0x12, BIT(0), 0x19, 0x1f,  700, 1900,  50, NA },
+	{ "eldo2", 0x12, BIT(1), 0x1a, 0x1f,  700, 1900,  50, NA },
+	{ "eldo3", 0x12, BIT(2), 0x1b, 0x1f,  700, 1900,  50, NA },
+	{ "fldo1", 0x13, BIT(2), 0x1c, 0x0f,  700, 1450,  50, NA },
+	{ "fldo2", 0x13, BIT(3), 0x1d, 0x0f,  700, 1450,  50, NA },
+	{ "dc1sw", 0x12, BIT(7),   NA,   NA,   NA,   NA,  NA, NA },
+	{ }
+};
+
+/*
+ * The "dcdcd" split changes the step size by a factor of 5, not 2;
+ * disallow values above the split to maintain accuracy.
+ */
+static const struct axp_regulator_plat axp806_regulators[] = {
+	{ "dcdca", 0x10, BIT(0), 0x12, 0x7f,  600, 1520,  10, 50 },
+	{ "dcdcb", 0x10, BIT(1), 0x13, 0x1f, 1000, 2550,  50, NA },
+	{ "dcdcc", 0x10, BIT(2), 0x14, 0x7f,  600, 1520,  10, 50 },
+	{ "dcdcd", 0x10, BIT(3), 0x15, 0x3f,  600, 1500,  20, NA },
+	{ "dcdce", 0x10, BIT(4), 0x16, 0x1f, 1100, 3400, 100, NA },
+	{ "aldo1", 0x10, BIT(5), 0x17, 0x1f,  700, 3300, 100, NA },
+	{ "aldo2", 0x10, BIT(6), 0x18, 0x1f,  700, 3300, 100, NA },
+	{ "aldo3", 0x10, BIT(7), 0x19, 0x1f,  700, 3300, 100, NA },
+	{ "bldo1", 0x11, BIT(0), 0x20, 0x0f,  700, 1900, 100, NA },
+	{ "bldo2", 0x11, BIT(1), 0x21, 0x0f,  700, 1900, 100, NA },
+	{ "bldo3", 0x11, BIT(2), 0x22, 0x0f,  700, 1900, 100, NA },
+	{ "bldo4", 0x11, BIT(3), 0x23, 0x0f,  700, 1900, 100, NA },
+	{ "cldo1", 0x11, BIT(4), 0x24, 0x1f,  700, 3300, 100, NA },
+	{ "cldo2", 0x11, BIT(5), 0x25, 0x1f,  700, 4200, 100, 27 },
+	{ "cldo3", 0x11, BIT(6), 0x26, 0x1f,  700, 3300, 100, NA },
+	{ "sw",    0x11, BIT(7),   NA,   NA,   NA,   NA,  NA, NA },
+	{ }
+};
+
+/*
+ * The "dcdc4" split changes the step size by a factor of 5, not 2;
+ * disallow values above the split to maintain accuracy.
+ */
+static const struct axp_regulator_plat axp809_regulators[] = {
+	{"dc5ldo", 0x10, BIT(0), 0x1c, 0x07,  700, 1400, 100, NA },
+	{ "dcdc1", 0x10, BIT(1), 0x21, 0x1f, 1600, 3400, 100, NA },
+	{ "dcdc2", 0x10, BIT(2), 0x22, 0x3f,  600, 1540,  20, NA },
+	{ "dcdc3", 0x10, BIT(3), 0x23, 0x3f,  600, 1860,  20, NA },
+	{ "dcdc4", 0x10, BIT(4), 0x24, 0x3f,  600, 1540,  20, NA },
+	{ "dcdc5", 0x10, BIT(5), 0x25, 0x1f, 1000, 2550,  50, NA },
+	{ "aldo1", 0x10, BIT(6), 0x28, 0x1f,  700, 3300, 100, NA },
+	{ "aldo2", 0x10, BIT(7), 0x29, 0x1f,  700, 3300, 100, NA },
+	{ "aldo3", 0x12, BIT(5), 0x2a, 0x1f,  700, 3300, 100, NA },
+	{ "dldo1", 0x12, BIT(3), 0x15, 0x1f,  700, 3300, 100, NA },
+	{ "dldo2", 0x12, BIT(4), 0x16, 0x1f,  700, 3300, 100, NA },
+	{ "eldo1", 0x12, BIT(0), 0x19, 0x1f,  700, 3300, 100, NA },
+	{ "eldo2", 0x12, BIT(1), 0x1a, 0x1f,  700, 3300, 100, NA },
+	{ "eldo3", 0x12, BIT(2), 0x1b, 0x1f,  700, 3300, 100, NA },
+	{ "sw",    0x12, BIT(6),   NA,   NA,   NA,   NA,  NA, NA },
+	{ "dc1sw", 0x12, BIT(7),   NA,   NA,   NA,   NA,  NA, NA },
+	{ }
+};
+
+static const struct axp_regulator_plat axp813_regulators[] = {
+	{ "dcdc1", 0x10, BIT(0), 0x20, 0x1f, 1600, 3400, 100, NA },
+	{ "dcdc2", 0x10, BIT(1), 0x21, 0x7f,  500, 1300,  10, 70 },
+	{ "dcdc3", 0x10, BIT(2), 0x22, 0x7f,  500, 1300,  10, 70 },
+	{ "dcdc4", 0x10, BIT(3), 0x23, 0x7f,  500, 1300,  10, 70 },
+	{ "dcdc5", 0x10, BIT(4), 0x24, 0x7f,  800, 1840,  10, 32 },
+	{ "dcdc6", 0x10, BIT(5), 0x25, 0x7f,  600, 1520,  10, 50 },
+	{ "dcdc7", 0x10, BIT(6), 0x26, 0x7f,  600, 1520,  10, 50 },
+	{ "aldo1", 0x13, BIT(5), 0x28, 0x1f,  700, 3300, 100, NA },
+	{ "aldo2", 0x13, BIT(6), 0x29, 0x1f,  700, 3300, 100, NA },
+	{ "aldo3", 0x13, BIT(7), 0x2a, 0x1f,  700, 3300, 100, NA },
+	{ "dldo1", 0x12, BIT(3), 0x15, 0x1f,  700, 3300, 100, NA },
+	{ "dldo2", 0x12, BIT(4), 0x16, 0x1f,  700, 4200, 100, 27 },
+	{ "dldo3", 0x12, BIT(5), 0x17, 0x1f,  700, 3300, 100, NA },
+	{ "dldo4", 0x12, BIT(6), 0x18, 0x1f,  700, 3300, 100, NA },
+	{ "eldo1", 0x12, BIT(0), 0x19, 0x1f,  700, 1900,  50, NA },
+	{ "eldo2", 0x12, BIT(1), 0x1a, 0x1f,  700, 1900,  50, NA },
+	{ "eldo3", 0x12, BIT(2), 0x1b, 0x1f,  700, 1900,  50, NA },
+	{ "fldo1", 0x13, BIT(2), 0x1c, 0x0f,  700, 1450,  50, NA },
+	{ "fldo2", 0x13, BIT(3), 0x1d, 0x0f,  700, 1450,  50, NA },
+	{ "fldo3", 0x13, BIT(4),   NA,   NA,   NA,   NA,  NA, NA },
+	{ }
+};
+
+static const struct axp_regulator_plat *const axp_regulators[] = {
+	[AXP152_ID]	= axp152_regulators,
+	[AXP202_ID]	= axp20x_regulators,
+	[AXP209_ID]	= axp20x_regulators,
+	[AXP221_ID]	= axp22x_regulators,
+	[AXP223_ID]	= axp22x_regulators,
+	[AXP803_ID]	= axp803_regulators,
+	[AXP806_ID]	= axp806_regulators,
+	[AXP809_ID]	= axp809_regulators,
+	[AXP813_ID]	= axp813_regulators,
+};
+
+static int axp_regulator_bind(struct udevice *dev)
+{
+	struct dm_regulator_uclass_plat *uc_plat = dev_get_uclass_plat(dev);
+	ulong id = dev_get_driver_data(dev->parent);
+	const struct axp_regulator_plat *plat;
+
+	for (plat = axp_regulators[id]; plat && plat->name; plat++)
+		if (!strcmp(plat->name, dev->name))
+			break;
+	if (!plat || !plat->name)
+		return -ENODEV;
+
+	dev_set_plat(dev, (void *)plat);
+
+	if (plat->volt_reg == NA)
+		uc_plat->type = REGULATOR_TYPE_FIXED;
+	else if (!strncmp(plat->name, "dcdc", strlen("dcdc")))
+		uc_plat->type = REGULATOR_TYPE_BUCK;
+	else
+		uc_plat->type = REGULATOR_TYPE_LDO;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(axp_regulator) = {
+	.name		= "axp_regulator",
+	.id		= UCLASS_REGULATOR,
+	.bind		= axp_regulator_bind,
+	.ops		= &axp_regulator_ops,
+};
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 19ed80b48a..4f5d098928 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -56,10 +56,10 @@ static int sunxi_dw_hdmi_get_divider(uint clock)
 		return 1;
 }
 
-static void sunxi_dw_hdmi_phy_init(void)
+static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi)
 {
 	struct sunxi_hdmi_phy * const phy =
-		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
+		(struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
 	unsigned long tmo;
 	u32 tmp;
 
@@ -113,10 +113,10 @@ static void sunxi_dw_hdmi_phy_init(void)
 	writel(0x42494E47, &phy->unscramble);
 }
 
-static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div)
+static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div)
 {
 	struct sunxi_hdmi_phy * const phy =
-		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
+		(struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
 	int div = sunxi_dw_hdmi_get_divider(clock);
 	u32 tmp;
 
@@ -270,7 +270,7 @@ static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
 	int phy_div;
 
 	sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
-	sunxi_dw_hdmi_phy_set(mpixelclock, phy_div);
+	sunxi_dw_hdmi_phy_set(hdmi, mpixelclock, phy_div);
 
 	return 0;
 }
@@ -291,10 +291,10 @@ static bool sunxi_dw_hdmi_mode_valid(struct udevice *dev,
 static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
 				const struct display_timing *edid)
 {
+	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 	struct sunxi_hdmi_phy * const phy =
-		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
+		(struct sunxi_hdmi_phy *)(priv->hdmi.ioaddr + HDMI_PHY_OFFS);
 	struct display_plat *uc_plat = dev_get_uclass_plat(dev);
-	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 	int ret;
 
 	ret = dw_hdmi_enable(&priv->hdmi, edid);
@@ -316,7 +316,7 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
 	 * again or othwerwise BSP driver won't work. Dummy read is
 	 * needed or otherwise last write doesn't get written correctly.
 	 */
-	(void)readb(SUNXI_HDMI_BASE);
+	(void)readb(priv->hdmi.ioaddr);
 	writel(0, &phy->unscramble);
 
 	return 0;
@@ -345,13 +345,7 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
 	/* Clock on */
 	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
 
-	sunxi_dw_hdmi_phy_init();
-
-	priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
-	priv->hdmi.i2c_clk_high = 0xd8;
-	priv->hdmi.i2c_clk_low = 0xfe;
-	priv->hdmi.reg_io_width = 1;
-	priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
+	sunxi_dw_hdmi_phy_init(&priv->hdmi);
 
 	ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi);
 	if (ret < 0) {
@@ -364,20 +358,37 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
 	return 0;
 }
 
+static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev)
+{
+	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
+	struct dw_hdmi *hdmi = &priv->hdmi;
+
+	hdmi->ioaddr = (ulong)dev_read_addr(dev);
+	hdmi->i2c_clk_high = 0xd8;
+	hdmi->i2c_clk_low = 0xfe;
+	hdmi->reg_io_width = 1;
+	hdmi->phy_set = sunxi_dw_hdmi_phy_cfg;
+
+	return 0;
+}
+
 static const struct dm_display_ops sunxi_dw_hdmi_ops = {
 	.read_edid = sunxi_dw_hdmi_read_edid,
 	.enable = sunxi_dw_hdmi_enable,
 	.mode_valid = sunxi_dw_hdmi_mode_valid,
 };
 
-U_BOOT_DRIVER(sunxi_dw_hdmi) = {
-	.name	= "sunxi_dw_hdmi",
-	.id	= UCLASS_DISPLAY,
-	.ops	= &sunxi_dw_hdmi_ops,
-	.probe	= sunxi_dw_hdmi_probe,
-	.priv_auto	= sizeof(struct sunxi_dw_hdmi_priv),
+static const struct udevice_id sunxi_dw_hdmi_ids[] = {
+	{ .compatible = "allwinner,sun8i-a83t-dw-hdmi" },
+	{ }
 };
 
-U_BOOT_DRVINFO(sunxi_dw_hdmi) = {
-	.name = "sunxi_dw_hdmi"
+U_BOOT_DRIVER(sunxi_dw_hdmi) = {
+	.name		= "sunxi_dw_hdmi",
+	.id		= UCLASS_DISPLAY,
+	.of_match	= sunxi_dw_hdmi_ids,
+	.probe		= sunxi_dw_hdmi_probe,
+	.of_to_plat	= sunxi_dw_hdmi_of_to_plat,
+	.priv_auto	= sizeof(struct sunxi_dw_hdmi_priv),
+	.ops		= &sunxi_dw_hdmi_ops,
 };