Merge branch 'for-2023.04' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx

- A fix for a long standing bug that has been exposed by commit
  50128aeb0f8 ("cyclic: get rid of cyclic_init()") preventing 8xx boards
  from booting since u-boot 2023.01
- A GPIO driver for powerpc 8xx chip
- Fixup for powerpc 8xx SPI driver
- A new powerpc 8xx board
- The two devices having that board.

4 files changed, 414 insertions, 37 deletions

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 365615a53f..7d5ddbdee0 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -547,6 +547,13 @@ config MPC8XXX_GPIO
 	  value setting, the open-drain feature, which can configure individual
 	  GPIOs to work as open-drain outputs, is supported.
 
+config MPC8XX_GPIO
+	bool "Freescale MPC8XX GPIO driver"
+	depends on DM_GPIO
+	help
+	  This driver supports parallel IO ports from MPC8XX CPUs.
+	  Each GPIO bank is identified by its own entry in the device tree.
+
 config MPC83XX_SPISEL_BOOT
 	bool "Freescale MPC83XX SPISEL_BOOT driver"
 	depends on DM_GPIO && ARCH_MPC830X
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fcd136367a..1e81e36962 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_TEGRA186_GPIO)	+= tegra186_gpio.o
 obj-$(CONFIG_DA8XX_GPIO)	+= da8xx_gpio.o
 obj-$(CONFIG_ALTERA_PIO)	+= altera_pio.o
 obj-$(CONFIG_MPC8XXX_GPIO)	+= mpc8xxx_gpio.o
+obj-$(CONFIG_MPC8XX_GPIO)	+= mpc8xx_gpio.o
 obj-$(CONFIG_MPC83XX_SPISEL_BOOT)	+= mpc83xx_spisel_boot.o
 obj-$(CONFIG_SH_GPIO_PFC)	+= sh_pfc.o
 obj-$(CONFIG_OMAP_GPIO)	+= omap_gpio.o
diff --git a/drivers/gpio/mpc8xx_gpio.c b/drivers/gpio/mpc8xx_gpio.c
new file mode 100644
index 0000000000..2f65346533
--- /dev/null
+++ b/drivers/gpio/mpc8xx_gpio.c
@@ -0,0 +1,347 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 CS Group
+ *	Charles Frey <charles.frey@c-s.fr>
+ *
+ * based on driver/gpio/mpc8xxx_gpio.c, which is
+ * Copyright 2016 Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
+ * Copyright 2010 eXMeritus, A Boeing Company
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <asm/gpio.h>
+#include <malloc.h>
+
+enum {
+	MPC8XX_CPM1_PORTA,
+	MPC8XX_CPM1_PORTB,
+	MPC8XX_CPM1_PORTC,
+	MPC8XX_CPM1_PORTD,
+	MPC8XX_CPM1_PORTE,
+};
+
+/*
+ * The MPC885 CPU CPM has 5 I/O ports, and each ports has different
+ * register length : 16 bits for ports A,C,D and 32 bits for ports
+ * B and E.
+ *
+ * This structure allows us to select the accessors according to the
+ * port we are configuring.
+ */
+struct mpc8xx_gpio_data {
+	/* The bank's register base in memory */
+	void __iomem *base;
+	/* The address of the registers; used to identify the bank */
+	ulong addr;
+	/* The GPIO count of the bank */
+	uint gpio_count;
+	/* Type needed to use the correct accessors */
+	int type;
+};
+
+/* Structure for ports A, C, D */
+struct iop_16 {
+	u16 pdir;
+	u16 ppar;
+	u16 podr;
+	u16 pdat;
+};
+
+/* Port B */
+struct iop_32_b {
+	u32 pdir;
+	u32 ppar;
+	u32 podr;
+	u32 pdat;
+};
+
+/* Port E */
+struct iop_32_e {
+	u32 pdir;
+	u32 ppar;
+	u32 psor;
+	u32 podr;
+	u32 pdat;
+};
+
+union iop_32 {
+	struct iop_32_b b;
+	struct iop_32_e e;
+};
+
+inline u32 gpio_mask(uint gpio, int type)
+{
+	if (type == MPC8XX_CPM1_PORTB || type == MPC8XX_CPM1_PORTE)
+		return 1U << (31 - (gpio));
+	else
+		return 1U << (15 - (gpio));
+}
+
+static inline u16 gpio16_get_val(void __iomem *base, u16 mask, int type)
+{
+	struct iop_16 *regs = base;
+
+	return in_be16(&regs->pdat) & mask;
+}
+
+static inline u16 gpio16_get_dir(void __iomem *base, u16 mask, int type)
+{
+	struct iop_16 *regs = base;
+
+	return in_be16(&regs->pdir) & mask;
+}
+
+static inline void gpio16_set_in(void __iomem *base, u16 gpios, int type)
+{
+	struct iop_16 *regs = base;
+
+	clrbits_be16(&regs->pdat, gpios);
+	/* GPDIR register 0 -> input */
+	clrbits_be16(&regs->pdir, gpios);
+}
+
+static inline void gpio16_set_lo(void __iomem *base, u16 gpios, int type)
+{
+	struct iop_16 *regs = base;
+
+	clrbits_be16(&regs->pdat, gpios);
+	/* GPDIR register 1 -> output */
+	setbits_be16(&regs->pdir, gpios);
+}
+
+static inline void gpio16_set_hi(void __iomem *base, u16 gpios, int type)
+{
+	struct iop_16 *regs = base;
+
+	setbits_be16(&regs->pdat, gpios);
+	/* GPDIR register 1 -> output */
+	setbits_be16(&regs->pdir, gpios);
+}
+
+/* PORT B AND E */
+static inline u32 gpio32_get_val(void __iomem *base, u32 mask, int type)
+{
+	union iop_32 __iomem *regs = base;
+
+	if (type == MPC8XX_CPM1_PORTB)
+		return in_be32(&regs->b.pdat) & mask;
+	else
+		return in_be32(&regs->e.pdat) & mask;
+}
+
+static inline u32 gpio32_get_dir(void __iomem *base, u32 mask, int type)
+{
+	union iop_32 __iomem *regs = base;
+
+	if (type == MPC8XX_CPM1_PORTB)
+		return in_be32(&regs->b.pdir) & mask;
+	else
+		return in_be32(&regs->e.pdir) & mask;
+}
+
+static inline void gpio32_set_in(void __iomem *base, u32 gpios, int type)
+{
+	union iop_32 __iomem *regs = base;
+
+	if (type == MPC8XX_CPM1_PORTB) {
+		clrbits_be32(&regs->b.pdat, gpios);
+		/* GPDIR register 0 -> input */
+		clrbits_be32(&regs->b.pdir, gpios);
+	} else { /* Port E */
+		clrbits_be32(&regs->e.pdat, gpios);
+		/* GPDIR register 0 -> input */
+		clrbits_be32(&regs->e.pdir, gpios);
+	}
+}
+
+static inline void gpio32_set_lo(void __iomem *base, u32 gpios, int type)
+{
+	union iop_32 __iomem *regs = base;
+
+	if (type == MPC8XX_CPM1_PORTB) {
+		clrbits_be32(&regs->b.pdat, gpios);
+		/* GPDIR register 1 -> output */
+		setbits_be32(&regs->b.pdir, gpios);
+	} else {
+		clrbits_be32(&regs->e.pdat, gpios);
+		/* GPDIR register 1 -> output */
+		setbits_be32(&regs->e.pdir, gpios);
+	}
+}
+
+static inline void gpio32_set_hi(void __iomem *base, u32 gpios, int type)
+{
+	union iop_32 __iomem *regs = base;
+
+	if (type == MPC8XX_CPM1_PORTB) {
+		setbits_be32(&regs->b.pdat, gpios);
+		/* GPDIR register 1 -> output */
+		setbits_be32(&regs->b.pdir, gpios);
+	} else {
+		setbits_be32(&regs->e.pdat, gpios);
+		/* GPDIR register 1 -> output */
+		setbits_be32(&regs->e.pdir, gpios);
+	}
+}
+
+static int mpc8xx_gpio_direction_input(struct udevice *dev, uint gpio)
+{
+	struct mpc8xx_gpio_data *data = dev_get_priv(dev);
+	int type = data->type;
+
+	if (type == MPC8XX_CPM1_PORTB || type == MPC8XX_CPM1_PORTE)
+		gpio32_set_in(data->base, gpio_mask(gpio, type), type);
+	else
+		gpio16_set_in(data->base, gpio_mask(gpio, type), type);
+
+	return 0;
+}
+
+static int mpc8xx_gpio_set_value(struct udevice *dev, uint gpio, int value)
+{
+	struct mpc8xx_gpio_data *data = dev_get_priv(dev);
+	int type = data->type;
+
+	if (type == MPC8XX_CPM1_PORTB || type == MPC8XX_CPM1_PORTE) {
+		if (value)
+			gpio32_set_hi(data->base, gpio_mask(gpio, type), type);
+		else
+			gpio32_set_lo(data->base, gpio_mask(gpio, type), type);
+	} else {
+		if (value)
+			gpio16_set_hi(data->base, gpio_mask(gpio, type), type);
+		else
+			gpio16_set_lo(data->base, gpio_mask(gpio, type), type);
+	}
+
+	return 0;
+}
+
+static int mpc8xx_gpio_direction_output(struct udevice *dev, uint gpio,
+					int value)
+{
+	return mpc8xx_gpio_set_value(dev, gpio, value);
+}
+
+static int mpc8xx_gpio_get_value(struct udevice *dev, uint gpio)
+{
+	struct mpc8xx_gpio_data *data = dev_get_priv(dev);
+	int type = data->type;
+
+	/* Input -> read value from GPDAT register */
+	if (type == MPC8XX_CPM1_PORTB || type == MPC8XX_CPM1_PORTE)
+		return gpio32_get_val(data->base, gpio_mask(gpio, type), type);
+	else
+		return gpio16_get_val(data->base, gpio_mask(gpio, type), type);
+}
+
+static int mpc8xx_gpio_get_function(struct udevice *dev, uint gpio)
+{
+	struct mpc8xx_gpio_data *data = dev_get_priv(dev);
+	int type = data->type;
+	int dir;
+
+	if (type == MPC8XX_CPM1_PORTB || type == MPC8XX_CPM1_PORTE)
+		dir = gpio32_get_dir(data->base, gpio_mask(gpio, type), type);
+	else
+		dir = gpio16_get_dir(data->base, gpio_mask(gpio, type), type);
+	return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
+}
+
+static int mpc8xx_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+	struct mpc8xx_gpio_plat *plat = dev_get_plat(dev);
+	fdt_addr_t addr;
+	u32 reg[2];
+
+	dev_read_u32_array(dev, "reg", reg, 2);
+	addr = dev_translate_address(dev, reg);
+
+	plat->addr = addr;
+	plat->size = reg[1];
+	plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
+
+	return 0;
+}
+
+static int mpc8xx_gpio_platdata_to_priv(struct udevice *dev)
+{
+	struct mpc8xx_gpio_data *priv = dev_get_priv(dev);
+	struct mpc8xx_gpio_plat *plat = dev_get_plat(dev);
+	unsigned long size = plat->size;
+	int type;
+
+	if (size == 0)
+		size = 0x100;
+
+	priv->addr = plat->addr;
+	priv->base = map_sysmem(plat->addr, size);
+
+	if (!priv->base)
+		return -ENOMEM;
+
+	priv->gpio_count = plat->ngpios;
+
+	type = dev_get_driver_data(dev);
+
+	if ((type == MPC8XX_CPM1_PORTA || type == MPC8XX_CPM1_PORTC ||
+	     type == MPC8XX_CPM1_PORTD) && plat->ngpios == 32)
+		priv->gpio_count = 16;
+
+	priv->type = type;
+
+	return 0;
+}
+
+static int mpc8xx_gpio_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct mpc8xx_gpio_data *data = dev_get_priv(dev);
+	char name[32], *str;
+
+	mpc8xx_gpio_platdata_to_priv(dev);
+
+	snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
+	str = strdup(name);
+
+	if (!str)
+		return -ENOMEM;
+
+	uc_priv->bank_name = str;
+	uc_priv->gpio_count = data->gpio_count;
+
+	return 0;
+}
+
+static const struct dm_gpio_ops gpio_mpc8xx_ops = {
+	.direction_input	= mpc8xx_gpio_direction_input,
+	.direction_output	= mpc8xx_gpio_direction_output,
+	.get_value		= mpc8xx_gpio_get_value,
+	.set_value		= mpc8xx_gpio_set_value,
+	.get_function		= mpc8xx_gpio_get_function,
+};
+
+static const struct udevice_id mpc8xx_gpio_ids[] = {
+	{ .compatible = "fsl,cpm1-pario-bank-a", .data = MPC8XX_CPM1_PORTA },
+	{ .compatible = "fsl,cpm1-pario-bank-b", .data = MPC8XX_CPM1_PORTB },
+	{ .compatible = "fsl,cpm1-pario-bank-c", .data = MPC8XX_CPM1_PORTC },
+	{ .compatible = "fsl,cpm1-pario-bank-d", .data = MPC8XX_CPM1_PORTD },
+	{ .compatible = "fsl,cpm1-pario-bank-e", .data = MPC8XX_CPM1_PORTE },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(gpio_mpc8xx) = {
+	.name	= "gpio_mpc8xx",
+	.id	= UCLASS_GPIO,
+	.ops	= &gpio_mpc8xx_ops,
+	.of_to_plat = mpc8xx_gpio_ofdata_to_platdata,
+	.plat_auto = sizeof(struct mpc8xx_gpio_plat),
+	.of_match = mpc8xx_gpio_ids,
+	.probe	= mpc8xx_gpio_probe,
+	.priv_auto = sizeof(struct mpc8xx_gpio_data),
+};
diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c
index 0026ad23e3..d84d7aea88 100644
--- a/drivers/spi/mpc8xx_spi.c
+++ b/drivers/spi/mpc8xx_spi.c
@@ -24,12 +24,29 @@
 
 #include <asm/cpm_8xx.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 
 #define CPM_SPI_BASE_RX	CPM_SPI_BASE
 #define CPM_SPI_BASE_TX	(CPM_SPI_BASE + sizeof(cbd_t))
 
 #define MAX_BUFFER	0x104
 
+struct mpc8xx_priv {
+	spi_t __iomem *spi;
+	struct gpio_desc gpios[16];
+	int max_cs;
+};
+
+static int mpc8xx_spi_set_mode(struct udevice *dev, uint mod)
+{
+	return 0;
+}
+
+static int mpc8xx_spi_set_speed(struct udevice *dev, uint speed)
+{
+	return 0;
+}
+
 static int mpc8xx_spi_probe(struct udevice *dev)
 {
 	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -38,42 +55,9 @@ static int mpc8xx_spi_probe(struct udevice *dev)
 	cbd_t __iomem *tbdf, *rbdf;
 
 	/* Disable relocation */
-	out_be16(&spi->spi_rpbase, 0);
+	out_be16(&spi->spi_rpbase, 0x1d80);
 
 /* 1 */
-	/* ------------------------------------------------
-	 * Initialize Port B SPI pins -> page 34-8 MPC860UM
-	 * (we are only in Master Mode !)
-	 * ------------------------------------------------ */
-
-	/* --------------------------------------------
-	 * GPIO or per. Function
-	 * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO)
-	 * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI)
-	 * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
-	 * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
-	 * -------------------------------------------- */
-	clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E);	/* set  bits */
-
-	/* ----------------------------------------------
-	 * In/Out or per. Function 0/1
-	 * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO
-	 * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI
-	 * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
-	 * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
-	 * ---------------------------------------------- */
-	setbits_be32(&cp->cp_pbdir, 0x0000000F);
-
-	/* ----------------------------------------------
-	 * open drain or active output
-	 * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
-	 * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
-	 * PBODR[30] = 0 [0x00000002] -> active output: SPICLK
-	 * PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM
-	 * ---------------------------------------------- */
-
-	clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
-
 	/* Initialize the parameter ram.
 	 * We need to make sure many things are initialized to zero
 	 */
@@ -143,6 +127,22 @@ static int mpc8xx_spi_probe(struct udevice *dev)
 	return 0;
 }
 
+static void mpc8xx_spi_cs_activate(struct udevice *dev)
+{
+	struct mpc8xx_priv *priv = dev_get_priv(dev->parent);
+	struct dm_spi_slave_plat *platdata = dev_get_parent_plat(dev);
+
+	dm_gpio_set_value(&priv->gpios[platdata->cs], 1);
+}
+
+static void mpc8xx_spi_cs_deactivate(struct udevice *dev)
+{
+	struct mpc8xx_priv *priv = dev_get_priv(dev->parent);
+	struct dm_spi_slave_plat *platdata = dev_get_parent_plat(dev);
+
+	dm_gpio_set_value(&priv->gpios[platdata->cs], 0);
+}
+
 static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
 			    const void *dout, void *din, unsigned long flags)
 {
@@ -159,7 +159,8 @@ static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
 
 	/* Set CS for device */
-	clrbits_be32(&cp->cp_pbdat, 0x0001);
+	if (flags & SPI_XFER_BEGIN)
+		mpc8xx_spi_cs_activate(dev);
 
 	/* Setting tx bd status and data length */
 	out_be32(&tbdf->cbd_bufaddr, (ulong)dout);
@@ -186,21 +187,40 @@ static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	for (tm = 0; tm < 1000; ++tm) {
 		if (in_8(&cp->cp_spie) & SPI_TXB)	/* Tx Buffer Empty */
 			break;
+
 		if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
 			break;
 		udelay(1000);
 	}
+
 	if (tm >= 1000)
 		printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
 
 	/* Clear CS for device */
-	setbits_be32(&cp->cp_pbdat, 0x0001);
+	if (flags & SPI_XFER_END)
+		mpc8xx_spi_cs_deactivate(dev);
 
-	return count;
+	return 0;
 }
 
+static int mpc8xx_spi_ofdata_to_platdata(struct udevice *dev)
+{
+	struct mpc8xx_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
+					ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT);
+	if (ret < 0)
+		return ret;
+
+	priv->max_cs = ret;
+
+	return 0;
+}
 static const struct dm_spi_ops mpc8xx_spi_ops = {
 	.xfer		= mpc8xx_spi_xfer,
+	.set_speed	= mpc8xx_spi_set_speed,
+	.set_mode	= mpc8xx_spi_set_mode,
 };
 
 static const struct udevice_id mpc8xx_spi_ids[] = {
@@ -212,6 +232,8 @@ U_BOOT_DRIVER(mpc8xx_spi) = {
 	.name	= "mpc8xx_spi",
 	.id	= UCLASS_SPI,
 	.of_match = mpc8xx_spi_ids,
+	.of_to_plat = mpc8xx_spi_ofdata_to_platdata,
 	.ops	= &mpc8xx_spi_ops,
 	.probe	= mpc8xx_spi_probe,
+	.priv_auto = sizeof(struct mpc8xx_priv),
 };