Merge tag 'v2023.04-rc3' into next

Prepare v2023.04-rc3

7 files changed, 68 insertions, 45 deletions

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 40f41a817c..6cb8c3e980 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -25,7 +25,6 @@ config L2X0_CACHE
 config V5L2_CACHE
 	bool "Andes V5L2 cache driver"
 	select CACHE
-	depends on RISCV_NDS_CACHE
 	help
 	  Support Andes V5L2 cache controller in AE350 platform.
 	  It will configure tag and data ram timing control from the
diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
index bbdb76bd57..eda07d3f29 100644
--- a/drivers/cache/cache-v5l2.c
+++ b/drivers/cache/cache-v5l2.c
@@ -34,6 +34,14 @@ struct l2cache {
 	volatile u64	cctl_status;
 };
 
+/* Configuration register */
+#define MEM_MAP_OFF	20
+#define MEM_MAP_MSK	BIT(MEM_MAP_OFF)
+/* offset of v0 memory map (Gen1) */
+static u32 cmd_stride = 0x10;
+static u32 status_stride = 0x0;
+static u32 status_bit_offset = 0x4;
+
 /* Control Register */
 #define L2_ENABLE	0x1
 /* prefetch */
@@ -53,14 +61,15 @@ struct l2cache {
 #define DRAMICTL_MSK	BIT(DRAMICTL_OFF)
 
 /* CCTL Command Register */
-#define CCTL_CMD_REG(base, hart)	((ulong)(base) + 0x40 + (hart) * 0x10)
+#define CCTL_CMD_REG(base, hart)	((ulong)(base) + 0x40 + (hart) * (cmd_stride))
 #define L2_WBINVAL_ALL	0x12
 
 /* CCTL Status Register */
-#define CCTL_STATUS_MSK(hart)		(0xf << ((hart) * 4))
-#define CCTL_STATUS_IDLE(hart)		(0 << ((hart) * 4))
-#define CCTL_STATUS_PROCESS(hart)	(1 << ((hart) * 4))
-#define CCTL_STATUS_ILLEGAL(hart)	(2 << ((hart) * 4))
+#define CCTL_STATUS_REG(base, hart)	((ulong)(base) + 0x80 + (hart) * (status_stride))
+#define CCTL_STATUS_MSK(hart)		(0xf << ((hart) * (status_bit_offset)))
+#define CCTL_STATUS_IDLE(hart)		(0 << ((hart) * (status_bit_offset)))
+#define CCTL_STATUS_PROCESS(hart)	(1 << ((hart) * (status_bit_offset)))
+#define CCTL_STATUS_ILLEGAL(hart)	(2 << ((hart) * (status_bit_offset)))
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -110,7 +119,7 @@ static int v5l2_of_to_plat(struct udevice *dev)
 	struct v5l2_plat *plat = dev_get_plat(dev);
 	struct l2cache *regs;
 
-	regs = (struct l2cache *)dev_read_addr(dev);
+	regs = (struct l2cache *)(uintptr_t)dev_read_addr(dev);
 	plat->regs = regs;
 
 	plat->iprefetch = -EINVAL;
@@ -133,12 +142,19 @@ static int v5l2_probe(struct udevice *dev)
 {
 	struct v5l2_plat *plat = dev_get_plat(dev);
 	struct l2cache *regs = plat->regs;
-	u32 ctl_val;
+	u32 cfg_val, ctl_val;
 
+	cfg_val = readl(&regs->configure);
 	ctl_val = readl(&regs->control);
 
-	if (!(ctl_val & L2_ENABLE))
-		ctl_val |= L2_ENABLE;
+	/* If true, v1 memory map (Gen2) */
+	if (cfg_val & MEM_MAP_MSK) {
+		cmd_stride = 0x1000;
+		status_stride = 0x1000;
+		status_bit_offset = 0x0;
+	}
+
+	ctl_val |= L2_ENABLE;
 
 	if (plat->iprefetch != -EINVAL) {
 		ctl_val &= ~(IPREPETCH_MSK);
@@ -168,7 +184,7 @@ static int v5l2_probe(struct udevice *dev)
 }
 
 static const struct udevice_id v5l2_cache_ids[] = {
-	{ .compatible = "v5l2cache" },
+	{ .compatible = "cache" },
 	{}
 };
 
diff --git a/drivers/net/ti/cpsw_mdio.c b/drivers/net/ti/cpsw_mdio.c
index a5ba73b739..ac791faa81 100644
--- a/drivers/net/ti/cpsw_mdio.c
+++ b/drivers/net/ti/cpsw_mdio.c
@@ -51,7 +51,7 @@ struct cpsw_mdio_regs {
 #define USERACCESS_PHY_REG_SHIFT	(21)
 #define USERACCESS_PHY_ADDR_SHIFT	(16)
 #define USERACCESS_DATA		GENMASK(15, 0)
-	} user[0];
+	} user[2];
 };
 
 #define CPSW_MDIO_DIV_DEF	0xff
@@ -366,8 +366,8 @@ u32 cpsw_mdio_get_alive(struct mii_dev *bus)
 	struct cpsw_mdio *mdio = bus->priv;
 	u32 val;
 
-	val = readl(&mdio->regs->control);
-	return val & GENMASK(15, 0);
+	val = readl(&mdio->regs->alive);
+	return val & GENMASK(7, 0);
 }
 
 struct mii_dev *cpsw_mdio_init(const char *name, phys_addr_t mdio_base,
diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c
index 36c35c608b..95fc26458b 100644
--- a/drivers/pwm/tegra_pwm.c
+++ b/drivers/pwm/tegra_pwm.c
@@ -20,19 +20,21 @@ static int tegra_pwm_set_config(struct udevice *dev, uint channel,
 {
 	struct tegra_pwm_priv *priv = dev_get_priv(dev);
 	struct pwm_ctlr *regs = priv->regs;
+	const u32 pwm_max_freq = dev_get_driver_data(dev);
 	uint pulse_width;
 	u32 reg;
 
 	if (channel >= 4)
 		return -EINVAL;
 	debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel);
-	/* We ignore the period here and just use 32KHz */
-	clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, 32768);
+
+	clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_PERIPH, pwm_max_freq);
 
 	pulse_width = duty_ns * 255 / period_ns;
 
 	reg = pulse_width << PWM_WIDTH_SHIFT;
 	reg |= 1 << PWM_DIVIDER_SHIFT;
+	reg |= PWM_ENABLE_MASK;
 	writel(reg, &regs[channel].control);
 	debug("%s: pulse_width=%u\n", __func__, pulse_width);
 
@@ -68,8 +70,8 @@ static const struct pwm_ops tegra_pwm_ops = {
 };
 
 static const struct udevice_id tegra_pwm_ids[] = {
-	{ .compatible = "nvidia,tegra124-pwm" },
-	{ .compatible = "nvidia,tegra20-pwm" },
+	{ .compatible = "nvidia,tegra20-pwm", .data = 48 * 1000000 },
+	{ .compatible = "nvidia,tegra114-pwm", .data = 408 * 1000000 },
 	{ }
 };
 
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index 209ba8b0cc..d0e788539e 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -208,16 +208,14 @@ static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	u32 reg, tmpdout, tmpdin = 0;
 	const u8 *dout = data_out;
 	u8 *din = data_in;
-	int num_bytes;
-	int ret;
+	int num_bytes, overflow;
+	int ret = 0;
 
 	debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
 	      __func__, dev_seq(bus), spi_chip_select(dev), dout, din, bitlen);
-	if (bitlen % 8)
-		return -1;
-	num_bytes = bitlen / 8;
 
-	ret = 0;
+	num_bytes = DIV_ROUND_UP(bitlen, 8);
+	overflow = bitlen % 8;
 
 	reg = readl(&regs->status);
 	writel(reg, &regs->status);	/* Clear all SPI events via R/W */
@@ -254,8 +252,13 @@ static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen,
 
 		num_bytes -= bytes;
 
-		clrsetbits_le32(&regs->command, SLINK_CMD_BIT_LENGTH_MASK,
-				bytes * 8 - 1);
+		if (overflow && !num_bytes)
+			clrsetbits_le32(&regs->command, SLINK_CMD_BIT_LENGTH_MASK,
+					(bytes - 1) * 8 + overflow - 1);
+		else
+			clrsetbits_le32(&regs->command, SLINK_CMD_BIT_LENGTH_MASK,
+					bytes * 8 - 1);
+
 		writel(tmpdout, &regs->tx_fifo);
 		setbits_le32(&regs->command, SLINK_CMD_GO);
 
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index acbf7acb19..66da5a8d6f 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -40,7 +40,7 @@ struct dwc3_generic_priv {
 	void *base;
 	struct dwc3 dwc3;
 	struct phy_bulk phys;
-	struct gpio_desc ulpi_reset;
+	struct gpio_desc *ulpi_reset;
 };
 
 struct dwc3_generic_host_priv {
@@ -104,23 +104,23 @@ static int dwc3_generic_probe(struct udevice *dev,
 
 	if (CONFIG_IS_ENABLED(DM_GPIO) &&
 	    device_is_compatible(dev->parent, "xlnx,zynqmp-dwc3")) {
-		rc = gpio_request_by_name(dev->parent, "reset-gpios", 0,
-					  &priv->ulpi_reset, GPIOD_ACTIVE_LOW);
-		if (rc)
-			return rc;
-
-		/* Toggle ulpi to reset the phy. */
-		rc = dm_gpio_set_value(&priv->ulpi_reset, 1);
-		if (rc)
-			return rc;
-
-		mdelay(5);
-
-		rc = dm_gpio_set_value(&priv->ulpi_reset, 0);
-		if (rc)
-			return rc;
-
-		mdelay(5);
+		priv->ulpi_reset = devm_gpiod_get_optional(dev->parent, "reset",
+								GPIOD_ACTIVE_LOW);
+		/* property is optional, don't return error! */
+		if (priv->ulpi_reset) {
+			/* Toggle ulpi to reset the phy. */
+			rc = dm_gpio_set_value(priv->ulpi_reset, 1);
+			if (rc)
+				return rc;
+
+			mdelay(5);
+
+			rc = dm_gpio_set_value(priv->ulpi_reset, 0);
+			if (rc)
+				return rc;
+
+			mdelay(5);
+		}
 	}
 
 	if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
@@ -146,7 +146,7 @@ static int dwc3_generic_remove(struct udevice *dev,
 
 	if (CONFIG_IS_ENABLED(DM_GPIO) &&
 	    device_is_compatible(dev->parent, "xlnx,zynqmp-dwc3")) {
-		struct gpio_desc *ulpi_reset = &priv->ulpi_reset;
+		struct gpio_desc *ulpi_reset = priv->ulpi_reset;
 
 		dm_gpio_free(ulpi_reset->dev, ulpi_reset);
 	}
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index e120efeb00..941f97c96d 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -40,6 +40,7 @@ if USB_GADGET
 
 config USB_GADGET_MANUFACTURER
 	string "Vendor name of the USB device"
+	default "NVIDIA" if ARCH_TEGRA
 	default "Allwinner Technology" if ARCH_SUNXI
 	default "Rockchip" if ARCH_ROCKCHIP
 	default "U-Boot"
@@ -49,6 +50,7 @@ config USB_GADGET_MANUFACTURER
 
 config USB_GADGET_VENDOR_NUM
 	hex "Vendor ID of the USB device"
+	default 0x0955 if ARCH_TEGRA
 	default 0x1f3a if ARCH_SUNXI
 	default 0x2207 if ARCH_ROCKCHIP
 	default 0x0
@@ -59,6 +61,7 @@ config USB_GADGET_VENDOR_NUM
 
 config USB_GADGET_PRODUCT_NUM
 	hex "Product ID of the USB device"
+	default 0x701a if ARCH_TEGRA
 	default 0x1010 if ARCH_SUNXI
 	default 0x310a if ROCKCHIP_RK3036
 	default 0x300a if ROCKCHIP_RK3066