diff options
| author | Weijie Gao <weijie.gao@mediatek.com> | 2021-01-12 08:44:02 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-01-18 23:23:06 +0300 |
| commit | 63779b240711cb1a0761bbceb323f5e9558394cc (patch) | |
| tree | 8f124e249c4e52a70e8d4940c0f0099f65425b47 /drivers | |
| parent | 97bf73762fed743291bb7e572aa659374990b93d (diff) | |
| download | u-boot-63779b240711cb1a0761bbceb323f5e9558394cc.tar.xz | |
timer: mtk_timer: initialize the timer before use
The timer being used by this driver may have already been used by first
stage bootloader (e.g. ATF/preloader), and it's settings may differ from
what this driver is going to use.
This may cause issues, such as inaccurate timer frequency due to
incorrect clock divider.
This patch adds the initialization code to avoid them.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/timer/mtk_timer.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c index 448a76a7e1..f6b97f868c 100644 --- a/drivers/timer/mtk_timer.c +++ b/drivers/timer/mtk_timer.c @@ -61,6 +61,16 @@ static int mtk_timer_probe(struct udevice *dev) if (!uc_priv->clock_rate) return -EINVAL; + /* + * Initialize the timer: + * 1. set clock source to system clock with clock divider setting to 1 + * 2. set timer mode to free running + * 3. reset timer counter to 0 then enable the timer + */ + writel(GPT4_CLK_SYS | GPT4_CLK_DIV1, priv->base + MTK_GPT4_CLK); + writel(GPT4_FREERUN | GPT4_CLEAR | GPT4_ENABLE, + priv->base + MTK_GPT4_CTRL); + return 0; } |