Merge tag 'xilinx-for-v2022.07-rc4' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.07-rc4

zynqmp:
- Fix DP PLL configuration for zcu102/zcu106 and SOM
- Fix split mode for starting R5s
- DT fixes
- Remove firmware node for mini configurations
- Wire TEE for multi DTB fit image

xilinx:
- Handle board_get_usable_ram_top(0) properly

phy:
- Extend psgtr timeout

mmc:
- Fix mini configuration which misses zynqmp_pm_is_function_supported()

4 files changed, 8 insertions, 3 deletions

diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index a59d96c6bd..e978b67988 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -79,6 +79,11 @@ __weak int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
 	return 0;
 }
 
+__weak int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
+{
+	return 1;
+}
+
 #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
 /* Default settings for ZynqMP Clock Phases */
 static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63,  0,
diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c
index 08c1b6efcf..d1288bb17f 100644
--- a/drivers/phy/phy-zynqmp.c
+++ b/drivers/phy/phy-zynqmp.c
@@ -168,7 +168,7 @@ enum {
 };
 
 /* Timeout values */
-#define TIMEOUT_US			1000
+#define TIMEOUT_US			10000
 
 #define IOU_SLCR_GEM_CLK_CTRL		0x308
 #define GEM_CTRL_GEM_SGMII_MODE		BIT(2)
diff --git a/drivers/soc/soc_xilinx_versal.c b/drivers/soc/soc_xilinx_versal.c
index f8bcd9ab40..3d8c25c19b 100644
--- a/drivers/soc/soc_xilinx_versal.c
+++ b/drivers/soc/soc_xilinx_versal.c
@@ -45,7 +45,7 @@ static const struct soc_ops soc_xilinx_versal_ops = {
 static int soc_xilinx_versal_probe(struct udevice *dev)
 {
 	struct soc_xilinx_versal_priv *priv = dev_get_priv(dev);
-	u32 ret_payload[4];
+	u32 ret_payload[PAYLOAD_ARG_CNT];
 	int ret;
 
 	priv->family = versal_family;
diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c
index 7d33ce2163..a71115b17c 100644
--- a/drivers/soc/soc_xilinx_zynqmp.c
+++ b/drivers/soc/soc_xilinx_zynqmp.c
@@ -49,7 +49,7 @@ static const struct soc_ops soc_xilinx_zynqmp_ops = {
 static int soc_xilinx_zynqmp_probe(struct udevice *dev)
 {
 	struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
-	u32 ret_payload[4];
+	u32 ret_payload[PAYLOAD_ARG_CNT];
 	int ret;
 
 	priv->family = zynqmp_family;