Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

- a37xx: pci: Cleanup and minor fix for root port check (Pali)
- pci: mvebu: Ensure that root port is always on root zero bus (Pali)
- kwbimage: Fix dumping DATA registers for v0 images (Pali)
- kwbimage: Support for parsing extended v0 format (Pali)
- a37xx: Fix code and update DTS files to upstream version (Pali)
- a37xx: Fix and extend building memory map (Pali)
- ddr: marvell: a38x: fix BYTE_HOMOGENEOUS_SPLIT_OUT decision (Marek)
- mvebu: Optionally reset board on DDR training failure (Marek)

8 files changed, 286 insertions, 333 deletions

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
index 42308b6965..be9f985f22 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
@@ -180,7 +180,8 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode)
 							       [bit_id],
 							       EDGE_1);
 					if (current_byte_status &
-					    BYTE_SPLIT_OUT_MIX) {
+					    (BYTE_SPLIT_OUT_MIX |
+					     BYTE_HOMOGENEOUS_SPLIT_OUT)) {
 						if (cur_start_win[bit_id] >= 64)
 							cur_start_win[bit_id] -= 64;
 						else
@@ -197,7 +198,8 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode)
 							       EDGE_1);
 					if (cur_end_win[bit_id] >= 64 &&
 					    (current_byte_status &
-					     BYTE_SPLIT_OUT_MIX)) {
+					     (BYTE_SPLIT_OUT_MIX |
+					      BYTE_HOMOGENEOUS_SPLIT_OUT))) {
 						cur_end_win[bit_id] -= 64;
 						DEBUG_CENTRALIZATION_ENGINE
 							(DEBUG_LEVEL_INFO,
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 22b6d8b628..4f7e61ecf1 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -35,136 +35,109 @@
 #include <linux/delay.h>
 #include <linux/ioport.h>
 
-/* PCIe core registers */
-#define PCIE_CORE_CMD_STATUS_REG				0x4
-#define     PCIE_CORE_CMD_IO_ACCESS_EN				BIT(0)
-#define     PCIE_CORE_CMD_MEM_ACCESS_EN				BIT(1)
-#define     PCIE_CORE_CMD_MEM_IO_REQ_EN				BIT(2)
-#define PCIE_CORE_DEV_REV_REG					0x8
-#define PCIE_CORE_EXP_ROM_BAR_REG				0x30
-#define PCIE_CORE_PCIEXP_CAP_OFF				0xc0
-#define PCIE_CORE_DEV_CTRL_STATS_REG				0xc8
-#define     PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE	(0 << 4)
-#define     PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE		(0 << 11)
-#define     PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE		0x2
-#define     PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT	5
-#define     PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE		0x2
-#define     PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT	12
-#define PCIE_CORE_LINK_CTRL_STAT_REG				0xd0
-#define     PCIE_CORE_LINK_TRAINING				BIT(5)
-#define PCIE_CORE_ERR_CAPCTL_REG				0x118
-#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX			BIT(5)
-#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN			BIT(6)
-#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHECK			BIT(7)
-#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV			BIT(8)
-
-/* PIO registers base address and register offsets */
-#define PIO_BASE_ADDR				0x4000
-#define PIO_CTRL				(PIO_BASE_ADDR + 0x0)
-#define   PIO_CTRL_TYPE_MASK			GENMASK(3, 0)
-#define   PIO_CTRL_ADDR_WIN_DISABLE		BIT(24)
-#define PIO_STAT				(PIO_BASE_ADDR + 0x4)
-#define   PIO_COMPLETION_STATUS_SHIFT		7
-#define   PIO_COMPLETION_STATUS_MASK		GENMASK(9, 7)
-#define   PIO_COMPLETION_STATUS_OK		0
-#define   PIO_COMPLETION_STATUS_UR		1
-#define   PIO_COMPLETION_STATUS_CRS		2
-#define   PIO_COMPLETION_STATUS_CA		4
-#define   PIO_NON_POSTED_REQ			BIT(10)
-#define   PIO_ERR_STATUS			BIT(11)
-#define PIO_ADDR_LS				(PIO_BASE_ADDR + 0x8)
-#define PIO_ADDR_MS				(PIO_BASE_ADDR + 0xc)
-#define PIO_WR_DATA				(PIO_BASE_ADDR + 0x10)
-#define PIO_WR_DATA_STRB			(PIO_BASE_ADDR + 0x14)
-#define PIO_RD_DATA				(PIO_BASE_ADDR + 0x18)
-#define PIO_START				(PIO_BASE_ADDR + 0x1c)
-#define PIO_ISR					(PIO_BASE_ADDR + 0x20)
-
-/* Aardvark Control registers */
-#define CONTROL_BASE_ADDR			0x4800
-#define PCIE_CORE_CTRL0_REG			(CONTROL_BASE_ADDR + 0x0)
-#define     PCIE_GEN_SEL_MSK			0x3
-#define     PCIE_GEN_SEL_SHIFT			0x0
-#define     SPEED_GEN_1				0
-#define     SPEED_GEN_2				1
-#define     SPEED_GEN_3				2
-#define     IS_RC_MSK				1
-#define     IS_RC_SHIFT				2
-#define     LANE_CNT_MSK			0x18
-#define     LANE_CNT_SHIFT			0x3
-#define     LANE_COUNT_1			(0 << LANE_CNT_SHIFT)
-#define     LANE_COUNT_2			(1 << LANE_CNT_SHIFT)
-#define     LANE_COUNT_4			(2 << LANE_CNT_SHIFT)
-#define     LANE_COUNT_8			(3 << LANE_CNT_SHIFT)
-#define     LINK_TRAINING_EN			BIT(6)
-#define PCIE_CORE_CTRL2_REG			(CONTROL_BASE_ADDR + 0x8)
-#define     PCIE_CORE_CTRL2_RESERVED		0x7
-#define     PCIE_CORE_CTRL2_TD_ENABLE		BIT(4)
-#define     PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE	BIT(5)
-#define     PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE	BIT(6)
-
-/* PCIe window configuration */
-#define OB_WIN_BASE_ADDR			0x4c00
-#define OB_WIN_BLOCK_SIZE			0x20
-#define OB_WIN_COUNT				8
-#define OB_WIN_REG_ADDR(win, offset)		(OB_WIN_BASE_ADDR + \
-						 OB_WIN_BLOCK_SIZE * (win) + \
-						 (offset))
-#define OB_WIN_MATCH_LS(win)			OB_WIN_REG_ADDR(win, 0x00)
-#define     OB_WIN_ENABLE			BIT(0)
-#define OB_WIN_MATCH_MS(win)			OB_WIN_REG_ADDR(win, 0x04)
-#define OB_WIN_REMAP_LS(win)			OB_WIN_REG_ADDR(win, 0x08)
-#define OB_WIN_REMAP_MS(win)			OB_WIN_REG_ADDR(win, 0x0c)
-#define OB_WIN_MASK_LS(win)			OB_WIN_REG_ADDR(win, 0x10)
-#define OB_WIN_MASK_MS(win)			OB_WIN_REG_ADDR(win, 0x14)
-#define OB_WIN_ACTIONS(win)			OB_WIN_REG_ADDR(win, 0x18)
-#define OB_WIN_DEFAULT_ACTIONS			(OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
-#define     OB_WIN_FUNC_NUM_MASK		GENMASK(31, 24)
-#define     OB_WIN_FUNC_NUM_SHIFT		24
-#define     OB_WIN_FUNC_NUM_ENABLE		BIT(23)
-#define     OB_WIN_BUS_NUM_BITS_MASK		GENMASK(22, 20)
-#define     OB_WIN_BUS_NUM_BITS_SHIFT		20
-#define     OB_WIN_MSG_CODE_ENABLE		BIT(22)
-#define     OB_WIN_MSG_CODE_MASK		GENMASK(21, 14)
-#define     OB_WIN_MSG_CODE_SHIFT		14
-#define     OB_WIN_MSG_PAYLOAD_LEN		BIT(12)
-#define     OB_WIN_ATTR_ENABLE			BIT(11)
-#define     OB_WIN_ATTR_TC_MASK			GENMASK(10, 8)
-#define     OB_WIN_ATTR_TC_SHIFT		8
-#define     OB_WIN_ATTR_RELAXED			BIT(7)
-#define     OB_WIN_ATTR_NOSNOOP			BIT(6)
-#define     OB_WIN_ATTR_POISON			BIT(5)
-#define     OB_WIN_ATTR_IDO			BIT(4)
-#define     OB_WIN_TYPE_MASK			GENMASK(3, 0)
-#define     OB_WIN_TYPE_SHIFT			0
-#define     OB_WIN_TYPE_MEM			0x0
-#define     OB_WIN_TYPE_IO			0x4
-#define     OB_WIN_TYPE_CONFIG_TYPE0		0x8
-#define     OB_WIN_TYPE_CONFIG_TYPE1		0x9
-#define     OB_WIN_TYPE_MSG			0xc
-
-/* LMI registers base address and register offsets */
-#define LMI_BASE_ADDR				0x6000
-#define CFG_REG					(LMI_BASE_ADDR + 0x0)
-#define     LTSSM_SHIFT				24
-#define     LTSSM_MASK				0x3f
-#define     LTSSM_L0				0x10
-#define     LTSSM_DISABLED			0x20
-#define VENDOR_ID_REG				(LMI_BASE_ADDR + 0x44)
-
-/* PCIe core controller registers */
-#define CTRL_CORE_BASE_ADDR			0x18000
-#define CTRL_CONFIG_REG				(CTRL_CORE_BASE_ADDR + 0x0)
-#define     CTRL_MODE_SHIFT			0x0
-#define     CTRL_MODE_MASK			0x1
-#define     PCIE_CORE_MODE_DIRECT		0x0
-#define     PCIE_CORE_MODE_COMMAND		0x1
-
-/* Transaction types */
-#define PCIE_CONFIG_RD_TYPE0			0x8
-#define PCIE_CONFIG_RD_TYPE1			0x9
-#define PCIE_CONFIG_WR_TYPE0			0xa
-#define PCIE_CONFIG_WR_TYPE1			0xb
+/* PCIe Root Port register offsets */
+#define ADVK_ROOT_PORT_PCI_CFG_OFF		0x0
+#define ADVK_ROOT_PORT_PCI_EXP_OFF		0xc0
+#define ADVK_ROOT_PORT_PCI_ERR_OFF		0x100
+
+/* PIO registers */
+#define ADVK_PIO_BASE_ADDR			0x4000
+#define ADVK_PIO_CTRL				(ADVK_PIO_BASE_ADDR + 0x0)
+#define   ADVK_PIO_CTRL_TYPE_MASK		GENMASK(3, 0)
+#define   ADVK_PIO_CTRL_TYPE_SHIFT		0
+#define   ADVK_PIO_CTRL_TYPE_RD_TYPE0		0x8
+#define   ADVK_PIO_CTRL_TYPE_RD_TYPE1		0x9
+#define   ADVK_PIO_CTRL_TYPE_WR_TYPE0		0xa
+#define   ADVK_PIO_CTRL_TYPE_WR_TYPE1		0xb
+#define   ADVK_PIO_CTRL_ADDR_WIN_DISABLE	BIT(24)
+#define ADVK_PIO_STAT				(ADVK_PIO_BASE_ADDR + 0x4)
+#define   ADVK_PIO_COMPLETION_STATUS_MASK	GENMASK(9, 7)
+#define   ADVK_PIO_COMPLETION_STATUS_SHIFT	7
+#define   ADVK_PIO_COMPLETION_STATUS_OK		0
+#define   ADVK_PIO_COMPLETION_STATUS_UR		1
+#define   ADVK_PIO_COMPLETION_STATUS_CRS	2
+#define   ADVK_PIO_COMPLETION_STATUS_CA		4
+#define   ADVK_PIO_NON_POSTED_REQ		BIT(10)
+#define   ADVK_PIO_ERR_STATUS			BIT(11)
+#define ADVK_PIO_ADDR_LS			(ADVK_PIO_BASE_ADDR + 0x8)
+#define ADVK_PIO_ADDR_MS			(ADVK_PIO_BASE_ADDR + 0xc)
+#define ADVK_PIO_WR_DATA			(ADVK_PIO_BASE_ADDR + 0x10)
+#define ADVK_PIO_WR_DATA_STRB			(ADVK_PIO_BASE_ADDR + 0x14)
+#define ADVK_PIO_RD_DATA			(ADVK_PIO_BASE_ADDR + 0x18)
+#define ADVK_PIO_START				(ADVK_PIO_BASE_ADDR + 0x1c)
+#define ADVK_PIO_ISR				(ADVK_PIO_BASE_ADDR + 0x20)
+
+/* Global Control registers */
+#define ADVK_GLOBAL_CTRL_BASE_ADDR		0x4800
+#define ADVK_GLOBAL_CTRL0			(ADVK_GLOBAL_CTRL_BASE_ADDR + 0x0)
+#define     ADVK_GLOBAL_CTRL0_SPEED_GEN_MASK	GENMASK(1, 0)
+#define     ADVK_GLOBAL_CTRL0_SPEED_GEN_SHIFT	0
+#define     ADVK_GLOBAL_CTRL0_SPEED_GEN_1	0
+#define     ADVK_GLOBAL_CTRL0_SPEED_GEN_2	1
+#define     ADVK_GLOBAL_CTRL0_SPEED_GEN_3	2
+#define     ADVK_GLOBAL_CTRL0_IS_RC		BIT(2)
+#define     ADVK_GLOBAL_CTRL0_LANE_COUNT_MASK	GENMASK(4, 3)
+#define     ADVK_GLOBAL_CTRL0_LANE_COUNT_SHIFT	3
+#define     ADVK_GLOBAL_CTRL0_LANE_COUNT_1	0
+#define     ADVK_GLOBAL_CTRL0_LANE_COUNT_2	1
+#define     ADVK_GLOBAL_CTRL0_LANE_COUNT_4	2
+#define     ADVK_GLOBAL_CTRL0_LANE_COUNT_8	3
+#define     ADVK_GLOBAL_CTRL0_LINK_TRAINING_EN	BIT(6)
+#define ADVK_GLOBAL_CTRL2			(ADVK_GLOBAL_CTRL_BASE_ADDR + 0x8)
+#define     ADVK_GLOBAL_CTRL2_STRICT_ORDER_EN	BIT(5)
+#define     ADVK_GLOBAL_CTRL2_ADDRWIN_MAP_EN	BIT(6)
+
+/* PCIe window configuration registers */
+#define ADVK_OB_WIN_BASE_ADDR			0x4c00
+#define ADVK_OB_WIN_BLOCK_SIZE			0x20
+#define ADVK_OB_WIN_COUNT			8
+#define ADVK_OB_WIN_REG_ADDR(win, offset)	(ADVK_OB_WIN_BASE_ADDR + ADVK_OB_WIN_BLOCK_SIZE * (win) + (offset))
+#define ADVK_OB_WIN_MATCH_LS(win)		ADVK_OB_WIN_REG_ADDR(win, 0x00)
+#define     ADVK_OB_WIN_ENABLE			BIT(0)
+#define ADVK_OB_WIN_MATCH_MS(win)		ADVK_OB_WIN_REG_ADDR(win, 0x04)
+#define ADVK_OB_WIN_REMAP_LS(win)		ADVK_OB_WIN_REG_ADDR(win, 0x08)
+#define ADVK_OB_WIN_REMAP_MS(win)		ADVK_OB_WIN_REG_ADDR(win, 0x0c)
+#define ADVK_OB_WIN_MASK_LS(win)		ADVK_OB_WIN_REG_ADDR(win, 0x10)
+#define ADVK_OB_WIN_MASK_MS(win)		ADVK_OB_WIN_REG_ADDR(win, 0x14)
+#define ADVK_OB_WIN_ACTIONS(win)		ADVK_OB_WIN_REG_ADDR(win, 0x18)
+#define ADVK_OB_WIN_DEFAULT_ACTIONS		(ADVK_OB_WIN_ACTIONS(ADVK_OB_WIN_COUNT-1) + 0x4)
+#define     ADVK_OB_WIN_FUNC_NUM_MASK		GENMASK(31, 24)
+#define     ADVK_OB_WIN_FUNC_NUM_SHIFT		24
+#define     ADVK_OB_WIN_FUNC_NUM_ENABLE		BIT(23)
+#define     ADVK_OB_WIN_BUS_NUM_BITS_MASK	GENMASK(22, 20)
+#define     ADVK_OB_WIN_BUS_NUM_BITS_SHIFT	20
+#define     ADVK_OB_WIN_MSG_CODE_ENABLE		BIT(22)
+#define     ADVK_OB_WIN_MSG_CODE_MASK		GENMASK(21, 14)
+#define     ADVK_OB_WIN_MSG_CODE_SHIFT		14
+#define     ADVK_OB_WIN_MSG_PAYLOAD_LEN		BIT(12)
+#define     ADVK_OB_WIN_ATTR_ENABLE		BIT(11)
+#define     ADVK_OB_WIN_ATTR_TC_MASK		GENMASK(10, 8)
+#define     ADVK_OB_WIN_ATTR_TC_SHIFT		8
+#define     ADVK_OB_WIN_ATTR_RELAXED		BIT(7)
+#define     ADVK_OB_WIN_ATTR_NOSNOOP		BIT(6)
+#define     ADVK_OB_WIN_ATTR_POISON		BIT(5)
+#define     ADVK_OB_WIN_ATTR_IDO		BIT(4)
+#define     ADVK_OB_WIN_TYPE_MASK		GENMASK(3, 0)
+#define     ADVK_OB_WIN_TYPE_SHIFT		0
+#define     ADVK_OB_WIN_TYPE_MEM		0x0
+#define     ADVK_OB_WIN_TYPE_IO			0x4
+#define     ADVK_OB_WIN_TYPE_CONFIG_TYPE0	0x8
+#define     ADVK_OB_WIN_TYPE_CONFIG_TYPE1	0x9
+#define     ADVK_OB_WIN_TYPE_MSG		0xc
+
+/* Local Management Interface registers */
+#define ADVK_LMI_BASE_ADDR			0x6000
+#define ADVK_LMI_PHY_CFG0			(ADVK_LMI_BASE_ADDR + 0x0)
+#define     ADVK_LMI_PHY_CFG0_LTSSM_MASK	GENMASK(29, 24)
+#define     ADVK_LMI_PHY_CFG0_LTSSM_SHIFT	24
+#define     ADVK_LMI_PHY_CFG0_LTSSM_L0		0x10
+#define     ADVK_LMI_PHY_CFG0_LTSSM_DISABLED	0x20
+#define ADVK_LMI_VENDOR_ID			(ADVK_LMI_BASE_ADDR + 0x44)
+
+/* Core Control registers */
+#define ADVK_CORE_CTRL_BASE_ADDR		0x18000
+#define ADVK_CORE_CTRL_CONFIG			(ADVK_CORE_CTRL_BASE_ADDR + 0x0)
+#define     ADVK_CORE_CTRL_CONFIG_COMMAND_MODE	BIT(0)
 
 /* PCIe Retries & Timeout definitions */
 #define PIO_MAX_RETRIES				1500
@@ -172,14 +145,12 @@
 #define LINK_MAX_RETRIES			10
 #define LINK_WAIT_TIMEOUT			100000
 
-#define CFG_RD_CRS_VAL			0xFFFF0001
+#define CFG_RD_CRS_VAL				0xFFFF0001
 
 /**
  * struct pcie_advk - Advk PCIe controller state
  *
  * @base:        The base address of the register space.
- * @first_busno: Bus number of the PCIe root-port.
- *               This may vary depending on the PCIe setup.
  * @sec_busno:   Bus number for the device behind the PCIe root-port.
  * @dev:         The pointer to PCI uclass device.
  * @reset_gpio:  GPIO descriptor for PERST.
@@ -189,7 +160,6 @@
  */
 struct pcie_advk {
 	void			*base;
-	int			first_busno;
 	int			sec_busno;
 	struct udevice		*dev;
 	struct gpio_desc	reset_gpio;
@@ -208,6 +178,23 @@ static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
 }
 
 /**
+ * pcie_advk_link_up() - Check if PCIe link is up or not
+ *
+ * @pcie: The PCI device to access
+ *
+ * Return true on link up.
+ * Return false on link down.
+ */
+static bool pcie_advk_link_up(struct pcie_advk *pcie)
+{
+	u32 val, ltssm_state;
+
+	val = advk_readl(pcie, ADVK_LMI_PHY_CFG0);
+	ltssm_state = (val & ADVK_LMI_PHY_CFG0_LTSSM_MASK) >> ADVK_LMI_PHY_CFG0_LTSSM_SHIFT;
+	return ltssm_state >= ADVK_LMI_PHY_CFG0_LTSSM_L0 && ltssm_state < ADVK_LMI_PHY_CFG0_LTSSM_DISABLED;
+}
+
+/**
  * pcie_advk_addr_valid() - Check for valid bus address
  *
  * @pcie: Pointer to the PCI bus
@@ -221,8 +208,12 @@ static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
 static bool pcie_advk_addr_valid(struct pcie_advk *pcie,
 				 int busno, u8 dev, u8 func)
 {
-	/* On the primary (local) bus there is only one PCI Bridge */
-	if (busno == pcie->first_busno && (dev != 0 || func != 0))
+	/* On the root bus there is only one PCI Bridge */
+	if (busno == 0 && (dev != 0 || func != 0))
+		return false;
+
+	/* Access to other buses is possible when link is up */
+	if (busno != 0 && !pcie_advk_link_up(pcie))
 		return false;
 
 	/*
@@ -252,8 +243,8 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie)
 	uint count;
 
 	for (count = 1; count <= PIO_MAX_RETRIES; count++) {
-		start = advk_readl(pcie, PIO_START);
-		isr = advk_readl(pcie, PIO_ISR);
+		start = advk_readl(pcie, ADVK_PIO_START);
+		isr = advk_readl(pcie, ADVK_PIO_ISR);
 		if (!start && isr)
 			return count;
 		/*
@@ -285,29 +276,29 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
 	unsigned int status;
 	char *strcomp_status, *str_posted;
 
-	reg = advk_readl(pcie, PIO_STAT);
-	status = (reg & PIO_COMPLETION_STATUS_MASK) >>
-		PIO_COMPLETION_STATUS_SHIFT;
+	reg = advk_readl(pcie, ADVK_PIO_STAT);
+	status = (reg & ADVK_PIO_COMPLETION_STATUS_MASK) >>
+		ADVK_PIO_COMPLETION_STATUS_SHIFT;
 
 	switch (status) {
-	case PIO_COMPLETION_STATUS_OK:
-		if (reg & PIO_ERR_STATUS) {
+	case ADVK_PIO_COMPLETION_STATUS_OK:
+		if (reg & ADVK_PIO_ERR_STATUS) {
 			strcomp_status = "COMP_ERR";
 			ret = -EFAULT;
 			break;
 		}
 		/* Get the read result */
 		if (read_val)
-			*read_val = advk_readl(pcie, PIO_RD_DATA);
+			*read_val = advk_readl(pcie, ADVK_PIO_RD_DATA);
 		/* No error */
 		strcomp_status = NULL;
 		ret = 0;
 		break;
-	case PIO_COMPLETION_STATUS_UR:
+	case ADVK_PIO_COMPLETION_STATUS_UR:
 		strcomp_status = "UR";
 		ret = -EOPNOTSUPP;
 		break;
-	case PIO_COMPLETION_STATUS_CRS:
+	case ADVK_PIO_COMPLETION_STATUS_CRS:
 		if (allow_crs && read_val) {
 			/* For reading, CRS is not an error status. */
 			*read_val = CFG_RD_CRS_VAL;
@@ -318,7 +309,7 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
 			ret = -EAGAIN;
 		}
 		break;
-	case PIO_COMPLETION_STATUS_CA:
+	case ADVK_PIO_COMPLETION_STATUS_CA:
 		strcomp_status = "CA";
 		ret = -ECANCELED;
 		break;
@@ -331,14 +322,14 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
 	if (!strcomp_status)
 		return ret;
 
-	if (reg & PIO_NON_POSTED_REQ)
+	if (reg & ADVK_PIO_NON_POSTED_REQ)
 		str_posted = "Non-posted";
 	else
 		str_posted = "Posted";
 
 	dev_dbg(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
 		str_posted, strcomp_status, reg,
-		advk_readl(pcie, PIO_ADDR_LS));
+		advk_readl(pcie, ADVK_PIO_ADDR_LS));
 
 	return ret;
 }
@@ -380,21 +371,21 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
 	}
 
 	/*
-	 * The configuration space of the PCI Bridge on primary (first) bus is
+	 * The configuration space of the PCI Bridge on the root bus (zero) is
 	 * not accessible via PIO transfers like all other PCIe devices. PCI
 	 * Bridge config registers are available directly in Aardvark memory
 	 * space starting at offset zero. The PCI Bridge config space is of
 	 * Type 0, but the BAR registers (including ROM BAR) don't have the same
 	 * meaning as in the PCIe specification. Therefore do not access BAR
 	 * registers and non-common registers (those which have different
-	 * meaning for Type 0 and Type 1 config space) of the primary PCI Bridge
+	 * meaning for Type 0 and Type 1 config space) of the PCI Bridge
 	 * and instead read their content from driver virtual cfgcache[].
 	 */
-	if (busno == pcie->first_busno) {
+	if (busno == 0) {
 		if ((offset >= 0x10 && offset < 0x34) || (offset >= 0x38 && offset < 0x3c))
 			data = pcie->cfgcache[(offset - 0x10) / 4];
 		else
-			data = advk_readl(pcie, offset & ~3);
+			data = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + (offset & ~3));
 
 		if ((offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
 			/*
@@ -406,14 +397,13 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
 			data |= PCI_HEADER_TYPE_BRIDGE << 16;
 		}
 
-		if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL) {
+		if ((offset & ~3) == ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_RTCTL) {
 			/* CRSSVE bit is stored only in cache */
 			if (pcie->cfgcrssve)
 				data |= PCI_EXP_RTCTL_CRSSVE;
 		}
 
-		if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF +
-				     (PCI_EXP_RTCAP & ~3)) {
+		if ((offset & ~3) == ADVK_ROOT_PORT_PCI_EXP_OFF + (PCI_EXP_RTCAP & ~3)) {
 			/* CRS is emulated below, so set CRSVIS capability */
 			data |= PCI_EXP_RTCAP_CRSVIS << 16;
 		}
@@ -437,7 +427,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
 	 */
 	allow_crs = (offset == PCI_VENDOR_ID) && (size == PCI_SIZE_32) && pcie->cfgcrssve;
 
-	if (advk_readl(pcie, PIO_START)) {
+	if (advk_readl(pcie, ADVK_PIO_START)) {
 		dev_err(pcie->dev,
 			"Previous PIO read/write transfer is still running\n");
 		if (allow_crs) {
@@ -449,28 +439,28 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
 	}
 
 	/* Program the control register */
-	reg = advk_readl(pcie, PIO_CTRL);
-	reg &= ~PIO_CTRL_TYPE_MASK;
+	reg = advk_readl(pcie, ADVK_PIO_CTRL);
+	reg &= ~ADVK_PIO_CTRL_TYPE_MASK;
 	if (busno == pcie->sec_busno)
-		reg |= PCIE_CONFIG_RD_TYPE0;
+		reg |= ADVK_PIO_CTRL_TYPE_RD_TYPE0 << ADVK_PIO_CTRL_TYPE_SHIFT;
 	else
-		reg |= PCIE_CONFIG_RD_TYPE1;
-	advk_writel(pcie, reg, PIO_CTRL);
+		reg |= ADVK_PIO_CTRL_TYPE_RD_TYPE1 << ADVK_PIO_CTRL_TYPE_SHIFT;
+	advk_writel(pcie, reg, ADVK_PIO_CTRL);
 
 	/* Program the address registers */
 	reg = PCIE_ECAM_OFFSET(busno, PCI_DEV(bdf), PCI_FUNC(bdf), (offset & ~0x3));
-	advk_writel(pcie, reg, PIO_ADDR_LS);
-	advk_writel(pcie, 0, PIO_ADDR_MS);
+	advk_writel(pcie, reg, ADVK_PIO_ADDR_LS);
+	advk_writel(pcie, 0, ADVK_PIO_ADDR_MS);
 
 	/* Program the data strobe */
-	advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
+	advk_writel(pcie, 0xf, ADVK_PIO_WR_DATA_STRB);
 
 	retry_count = 0;
 
 retry:
 	/* Start the transfer */
-	advk_writel(pcie, 1, PIO_ISR);
-	advk_writel(pcie, 1, PIO_START);
+	advk_writel(pcie, 1, ADVK_PIO_ISR);
+	advk_writel(pcie, 1, ADVK_PIO_START);
 
 	ret = pcie_advk_wait_pio(pcie);
 	if (ret < 0) {
@@ -571,7 +561,7 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
 	 * zero. Type 1 specific registers are not available, so we write their
 	 * content only into driver virtual cfgcache[].
 	 */
-	if (busno == pcie->first_busno) {
+	if (busno == 0) {
 		if ((offset >= 0x10 && offset < 0x34) ||
 		    (offset >= 0x38 && offset < 0x3c)) {
 			data = pcie->cfgcache[(offset - 0x10) / 4];
@@ -583,61 +573,58 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
 				data = 0x0;
 			pcie->cfgcache[(offset - 0x10) / 4] = data;
 		} else {
-			data = advk_readl(pcie, offset & ~3);
+			data = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + (offset & ~3));
 			data = pci_conv_size_to_32(data, value, offset, size);
-			advk_writel(pcie, data, offset & ~3);
+			advk_writel(pcie, data, ADVK_ROOT_PORT_PCI_CFG_OFF + (offset & ~3));
 		}
 
-		if (offset == PCI_PRIMARY_BUS)
-			pcie->first_busno = data & 0xff;
-
 		if (offset == PCI_SECONDARY_BUS ||
 		    (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))
 			pcie->sec_busno = (data >> 8) & 0xff;
 
-		if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL)
+		if ((offset & ~3) == ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_RTCTL)
 			pcie->cfgcrssve = data & PCI_EXP_RTCTL_CRSSVE;
 
 		return 0;
 	}
 
-	if (advk_readl(pcie, PIO_START)) {
+	if (advk_readl(pcie, ADVK_PIO_START)) {
 		dev_err(pcie->dev,
 			"Previous PIO read/write transfer is still running\n");
 		return -EAGAIN;
 	}
 
 	/* Program the control register */
-	reg = advk_readl(pcie, PIO_CTRL);
-	reg &= ~PIO_CTRL_TYPE_MASK;
+	reg = advk_readl(pcie, ADVK_PIO_CTRL);
+	reg &= ~ADVK_PIO_CTRL_TYPE_MASK;
 	if (busno == pcie->sec_busno)
-		reg |= PCIE_CONFIG_WR_TYPE0;
+		reg |= ADVK_PIO_CTRL_TYPE_WR_TYPE0 << ADVK_PIO_CTRL_TYPE_SHIFT;
 	else
-		reg |= PCIE_CONFIG_WR_TYPE1;
-	advk_writel(pcie, reg, PIO_CTRL);
+		reg |= ADVK_PIO_CTRL_TYPE_WR_TYPE1 << ADVK_PIO_CTRL_TYPE_SHIFT;
+	advk_writel(pcie, reg, ADVK_PIO_CTRL);
 
 	/* Program the address registers */
 	reg = PCIE_ECAM_OFFSET(busno, PCI_DEV(bdf), PCI_FUNC(bdf), (offset & ~0x3));
-	advk_writel(pcie, reg, PIO_ADDR_LS);
-	advk_writel(pcie, 0, PIO_ADDR_MS);
+	advk_writel(pcie, reg, ADVK_PIO_ADDR_LS);
+	advk_writel(pcie, 0, ADVK_PIO_ADDR_MS);
 	dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
 
 	/* Program the data register */
 	reg = pci_conv_size_to_32(0, value, offset, size);
-	advk_writel(pcie, reg, PIO_WR_DATA);
+	advk_writel(pcie, reg, ADVK_PIO_WR_DATA);
 	dev_dbg(pcie->dev, "\tPIO req. - val  = 0x%08x\n", reg);
 
 	/* Program the data strobe */
 	reg = pcie_calc_datastrobe(offset, size);
-	advk_writel(pcie, reg, PIO_WR_DATA_STRB);
+	advk_writel(pcie, reg, ADVK_PIO_WR_DATA_STRB);
 	dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
 
 	retry_count = 0;
 
 retry:
 	/* Start the transfer */
-	advk_writel(pcie, 1, PIO_ISR);
-	advk_writel(pcie, 1, PIO_START);
+	advk_writel(pcie, 1, ADVK_PIO_ISR);
+	advk_writel(pcie, 1, ADVK_PIO_START);
 
 	ret = pcie_advk_wait_pio(pcie);
 	if (ret < 0)
@@ -653,33 +640,13 @@ retry:
 }
 
 /**
- * pcie_advk_link_up() - Check if PCIe link is up or not
- *
- * @pcie: The PCI device to access
- *
- * Return 1 (true) on link up.
- * Return 0 (false) on link down.
- */
-static int pcie_advk_link_up(struct pcie_advk *pcie)
-{
-	u32 val, ltssm_state;
-
-	val = advk_readl(pcie, CFG_REG);
-	ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
-	return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED;
-}
-
-/**
  * pcie_advk_wait_for_link() - Wait for link training to be accomplished
  *
  * @pcie: The PCI device to access
  *
  * Wait up to 1 second for link training to be accomplished.
- *
- * Return 1 (true) if link training ends up with link up success.
- * Return 0 (false) if link training ends up with link up failure.
  */
-static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
+static void pcie_advk_wait_for_link(struct pcie_advk *pcie)
 {
 	int retries;
 
@@ -687,15 +654,13 @@ static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
 	for (retries = 0; retries < LINK_MAX_RETRIES; retries++) {
 		if (pcie_advk_link_up(pcie)) {
 			printf("PCIe: Link up\n");
-			return 0;
+			return;
 		}
 
 		udelay(LINK_WAIT_TIMEOUT);
 	}
 
 	printf("PCIe: Link down\n");
-
-	return -ETIMEDOUT;
 }
 
 /*
@@ -706,25 +671,25 @@ static void pcie_advk_set_ob_win(struct pcie_advk *pcie, u8 win_num,
 				 phys_addr_t match, phys_addr_t remap,
 				 phys_addr_t mask, u32 actions)
 {
-	advk_writel(pcie, OB_WIN_ENABLE |
-			  lower_32_bits(match), OB_WIN_MATCH_LS(win_num));
-	advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num));
-	advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num));
-	advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num));
-	advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num));
-	advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num));
-	advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num));
+	advk_writel(pcie, ADVK_OB_WIN_ENABLE |
+			  lower_32_bits(match), ADVK_OB_WIN_MATCH_LS(win_num));
+	advk_writel(pcie, upper_32_bits(match), ADVK_OB_WIN_MATCH_MS(win_num));
+	advk_writel(pcie, lower_32_bits(remap), ADVK_OB_WIN_REMAP_LS(win_num));
+	advk_writel(pcie, upper_32_bits(remap), ADVK_OB_WIN_REMAP_MS(win_num));
+	advk_writel(pcie, lower_32_bits(mask), ADVK_OB_WIN_MASK_LS(win_num));
+	advk_writel(pcie, upper_32_bits(mask), ADVK_OB_WIN_MASK_MS(win_num));
+	advk_writel(pcie, actions, ADVK_OB_WIN_ACTIONS(win_num));
 }
 
 static void pcie_advk_disable_ob_win(struct pcie_advk *pcie, u8 win_num)
 {
-	advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num));
-	advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num));
-	advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num));
-	advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num));
-	advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num));
-	advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num));
-	advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num));
+	advk_writel(pcie, 0, ADVK_OB_WIN_MATCH_LS(win_num));
+	advk_writel(pcie, 0, ADVK_OB_WIN_MATCH_MS(win_num));
+	advk_writel(pcie, 0, ADVK_OB_WIN_REMAP_LS(win_num));
+	advk_writel(pcie, 0, ADVK_OB_WIN_REMAP_MS(win_num));
+	advk_writel(pcie, 0, ADVK_OB_WIN_MASK_LS(win_num));
+	advk_writel(pcie, 0, ADVK_OB_WIN_MASK_MS(win_num));
+	advk_writel(pcie, 0, ADVK_OB_WIN_ACTIONS(win_num));
 }
 
 static void pcie_advk_set_ob_region(struct pcie_advk *pcie, int *wins,
@@ -748,7 +713,7 @@ static void pcie_advk_set_ob_region(struct pcie_advk *pcie, int *wins,
 	 * because lower 16 bits of mask must be zero. Remapped address
 	 * may have set only bits from the mask.
 	 */
-	while (*wins < OB_WIN_COUNT && size > 0) {
+	while (*wins < ADVK_OB_WIN_COUNT && size > 0) {
 		/* Calculate the largest aligned window size */
 		win_size = (1ULL << (fls64(size) - 1)) |
 			   (phys_start ? (1ULL << __ffs64(phys_start)) : 0);
@@ -792,25 +757,24 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
 	int i, wins;
 	u32 reg;
 
-	/* Set to Direct mode */
-	reg = advk_readl(pcie, CTRL_CONFIG_REG);
-	reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
-	reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
-	advk_writel(pcie, reg, CTRL_CONFIG_REG);
+	/* Set from Command to Direct mode */
+	reg = advk_readl(pcie, ADVK_CORE_CTRL_CONFIG);
+	reg &= ~ADVK_CORE_CTRL_CONFIG_COMMAND_MODE;
+	advk_writel(pcie, reg, ADVK_CORE_CTRL_CONFIG);
 
 	/* Set PCI global control register to RC mode */
-	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
-	reg |= (IS_RC_MSK << IS_RC_SHIFT);
-	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+	reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
+	reg |= ADVK_GLOBAL_CTRL0_IS_RC;
+	advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
 
 	/*
 	 * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab.
-	 * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor
+	 * ADVK_LMI_VENDOR_ID contains vendor id in low 16 bits and subsystem vendor
 	 * id in high 16 bits. Updating this register changes readback value of
-	 * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround
+	 * read-only vendor id bits in Root Port PCI_VENDOR_ID register. Workaround
 	 * for erratum 4.1: "The value of device and vendor ID is incorrect".
 	 */
-	advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG);
+	advk_writel(pcie, 0x11ab11ab, ADVK_LMI_VENDOR_ID);
 
 	/*
 	 * Change Class Code of PCI Bridge device to PCI Bridge (0x600400),
@@ -834,48 +798,47 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
 	 * Type 1 registers is redirected to the virtual cfgcache[] buffer,
 	 * which avoids changing unrelated registers.
 	 */
-	reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG);
+	reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
 	reg &= ~0xffffff00;
 	reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
-	advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG);
-
-	/* Set Advanced Error Capabilities and Control PF0 register */
-	reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
-		PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
-		PCIE_CORE_ERR_CAPCTL_ECRC_CHECK |
-		PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV;
-	advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
-
-	/* Set PCIe Device Control and Status 1 PF0 register */
-	reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
-		(PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE <<
-		 PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT) |
-		(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE <<
-		 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT) |
-		PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
-	advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
+	advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
+
+	/* Enable generation and checking of ECRC on PCIe Root Port */
+	reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_ERR_OFF + PCI_ERR_CAP);
+	reg |= PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE;
+	advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_ERR_OFF + PCI_ERR_CAP);
+
+	/* Set PCIe Device Control register on PCIe Root Port */
+	reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_DEVCTL);
+	reg &= ~PCI_EXP_DEVCTL_RELAX_EN;
+	reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
+	reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
+	reg &= ~PCI_EXP_DEVCTL_READRQ;
+	reg |= PCI_EXP_DEVCTL_PAYLOAD_512B;
+	reg |= PCI_EXP_DEVCTL_READRQ_512B;
+	advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_DEVCTL);
 
 	/* Program PCIe Control 2 to disable strict ordering */
-	reg = PCIE_CORE_CTRL2_RESERVED |
-		PCIE_CORE_CTRL2_TD_ENABLE;
-	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
+	reg = advk_readl(pcie, ADVK_GLOBAL_CTRL2);
+	reg &= ~ADVK_GLOBAL_CTRL2_STRICT_ORDER_EN;
+	advk_writel(pcie, reg, ADVK_GLOBAL_CTRL2);
 
 	/* Set GEN2 */
-	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
-	reg &= ~PCIE_GEN_SEL_MSK;
-	reg |= SPEED_GEN_2;
-	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+	reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
+	reg &= ~ADVK_GLOBAL_CTRL0_SPEED_GEN_MASK;
+	reg |= ADVK_GLOBAL_CTRL0_SPEED_GEN_2 << ADVK_GLOBAL_CTRL0_SPEED_GEN_SHIFT;
+	advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
 
 	/* Set lane X1 */
-	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
-	reg &= ~LANE_CNT_MSK;
-	reg |= LANE_COUNT_1;
-	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+	reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
+	reg &= ~ADVK_GLOBAL_CTRL0_LANE_COUNT_MASK;
+	reg |= ADVK_GLOBAL_CTRL0_LANE_COUNT_1 << ADVK_GLOBAL_CTRL0_LANE_COUNT_SHIFT;
+	advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
 
 	/* Enable link training */
-	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
-	reg |= LINK_TRAINING_EN;
-	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+	reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
+	reg |= ADVK_GLOBAL_CTRL0_LINK_TRAINING_EN;
+	advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
 
 	/*
 	 * Enable AXI address window location generation:
@@ -887,9 +850,9 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
 	 * access when default outbound window configuration
 	 * is set for memory access.
 	 */
-	reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
-	reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
-	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
+	reg = advk_readl(pcie, ADVK_GLOBAL_CTRL2);
+	reg |= ADVK_GLOBAL_CTRL2_ADDRWIN_MAP_EN;
+	advk_writel(pcie, reg, ADVK_GLOBAL_CTRL2);
 
 	/*
 	 * Bypass the address window mapping for PIO:
@@ -897,16 +860,16 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
 	 * info over AXI interface by PIO registers, the
 	 * address window is not required.
 	 */
-	reg = advk_readl(pcie, PIO_CTRL);
-	reg |= PIO_CTRL_ADDR_WIN_DISABLE;
-	advk_writel(pcie, reg, PIO_CTRL);
+	reg = advk_readl(pcie, ADVK_PIO_CTRL);
+	reg |= ADVK_PIO_CTRL_ADDR_WIN_DISABLE;
+	advk_writel(pcie, reg, ADVK_PIO_CTRL);
 
 	/*
 	 * Set memory access in Default User Field so it
 	 * is not required to configure PCIe address for
 	 * transparent memory access.
 	 */
-	advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS);
+	advk_writel(pcie, ADVK_OB_WIN_TYPE_MEM, ADVK_OB_WIN_DEFAULT_ACTIONS);
 
 	/*
 	 * Configure PCIe address windows for non-memory or
@@ -916,22 +879,21 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
 	wins = 0;
 	pci_get_regions(pcie->dev, &io, &mem, &pref);
 	if (io)
-		pcie_advk_set_ob_region(pcie, &wins, io, OB_WIN_TYPE_IO);
+		pcie_advk_set_ob_region(pcie, &wins, io, ADVK_OB_WIN_TYPE_IO);
 	if (mem && mem->phys_start != mem->bus_start)
-		pcie_advk_set_ob_region(pcie, &wins, mem, OB_WIN_TYPE_MEM);
+		pcie_advk_set_ob_region(pcie, &wins, mem, ADVK_OB_WIN_TYPE_MEM);
 	if (pref && pref->phys_start != pref->bus_start)
-		pcie_advk_set_ob_region(pcie, &wins, pref, OB_WIN_TYPE_MEM);
+		pcie_advk_set_ob_region(pcie, &wins, pref, ADVK_OB_WIN_TYPE_MEM);
 
 	/* Disable remaining PCIe outbound windows */
-	for (i = ((wins >= 0) ? wins : 0); i < OB_WIN_COUNT; i++)
+	for (i = ((wins >= 0) ? wins : 0); i < ADVK_OB_WIN_COUNT; i++)
 		pcie_advk_disable_ob_win(pcie, i);
 
 	if (wins == -1)
 		return -EINVAL;
 
 	/* Wait for PCIe link up */
-	if (pcie_advk_wait_for_link(pcie))
-		return -ENXIO;
+	pcie_advk_wait_for_link(pcie);
 
 	return 0;
 }
@@ -991,18 +953,16 @@ static int pcie_advk_remove(struct udevice *dev)
 	u32 reg;
 	int i;
 
-	for (i = 0; i < OB_WIN_COUNT; i++)
+	for (i = 0; i < ADVK_OB_WIN_COUNT; i++)
 		pcie_advk_disable_ob_win(pcie, i);
 
-	reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
-	reg &= ~(PCIE_CORE_CMD_MEM_ACCESS_EN |
-		 PCIE_CORE_CMD_IO_ACCESS_EN |
-		 PCIE_CORE_CMD_MEM_IO_REQ_EN);
-	advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
+	reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_COMMAND);
+	reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+	advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_COMMAND);
 
-	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
-	reg &= ~LINK_TRAINING_EN;
-	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+	reg = advk_readl(pcie, ADVK_GLOBAL_CTRL0);
+	reg &= ~ADVK_GLOBAL_CTRL0_LINK_TRAINING_EN;
+	advk_writel(pcie, reg, ADVK_GLOBAL_CTRL0);
 
 	return 0;
 }
@@ -1023,7 +983,7 @@ static int pcie_advk_of_to_plat(struct udevice *dev)
 	struct pcie_advk *pcie = dev_get_priv(dev);
 
 	/* Get the register base address */
-	pcie->base = (void *)dev_read_addr_index(dev, 0);
+	pcie->base = (void *)dev_read_addr(dev);
 	if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index d99a99bae9..5a0a59a8b9 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -78,7 +78,6 @@ struct mvebu_pcie {
 	bool is_x4;
 	int devfn;
 	u32 lane_mask;
-	int first_busno;
 	int sec_busno;
 	char name[16];
 	unsigned int mem_target;
@@ -140,12 +139,12 @@ static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
 static bool mvebu_pcie_valid_addr(struct mvebu_pcie *pcie,
 				  int busno, int dev, int func)
 {
-	/* On primary bus is only one PCI Bridge */
-	if (busno == pcie->first_busno && (dev != 0 || func != 0))
+	/* On the root bus is only one PCI Bridge */
+	if (busno == 0 && (dev != 0 || func != 0))
 		return false;
 
 	/* Access to other buses is possible when link is up */
-	if (busno != pcie->first_busno && !mvebu_pcie_link_up(pcie))
+	if (busno != 0 && !mvebu_pcie_link_up(pcie))
 		return false;
 
 	/* On secondary bus can be only one PCIe device */
@@ -173,15 +172,15 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
 	}
 
 	/*
-	 * The configuration space of the PCI Bridge on primary (first) bus is
+	 * The configuration space of the PCI Bridge on the root bus (zero) is
 	 * of Type 0 but the BAR registers (including ROM BAR) don't have the
 	 * same meaning as in the PCIe specification. Therefore do not access
 	 * BAR registers and non-common registers (those which have different
 	 * meaning for Type 0 and Type 1 config space) of the PCI Bridge and
 	 * instead read their content from driver virtual cfgcache[].
 	 */
-	if (busno == pcie->first_busno && ((offset >= 0x10 && offset < 0x34) ||
-					   (offset >= 0x38 && offset < 0x3c))) {
+	if (busno == 0 && ((offset >= 0x10 && offset < 0x34) ||
+			   (offset >= 0x38 && offset < 0x3c))) {
 		data = pcie->cfgcache[(offset - 0x10) / 4];
 		debug("(addr,size,val)=(0x%04x, %d, 0x%08x) from cfgcache\n",
 		      offset, size, data);
@@ -190,10 +189,10 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
 	}
 
 	/*
-	 * PCI bridge is device 0 at primary bus but mvebu has it mapped on
-	 * secondary bus with device number 1.
+	 * PCI bridge is device 0 at the root bus (zero) but mvebu has it
+	 * mapped on secondary bus with device number 1.
 	 */
-	if (busno == pcie->first_busno)
+	if (busno == 0)
 		addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset);
 	else
 		addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
@@ -216,8 +215,7 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
 		return -EINVAL;
 	}
 
-	if (busno == pcie->first_busno &&
-	    (offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
+	if (busno == 0 && (offset & ~3) == (PCI_HEADER_TYPE & ~3)) {
 		/*
 		 * Change Header Type of PCI Bridge device to Type 1
 		 * (0x01, used by PCI Bridges) because mvebu reports
@@ -257,10 +255,10 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
 	 * config registers are not available, so we write their content only
 	 * into driver virtual cfgcache[].
 	 * And as explained in mvebu_pcie_probe(), mvebu has its own specific
-	 * way for configuring primary and secondary bus numbers.
+	 * way for configuring secondary bus number.
 	 */
-	if (busno == pcie->first_busno && ((offset >= 0x10 && offset < 0x34) ||
-					   (offset >= 0x38 && offset < 0x3c))) {
+	if (busno == 0 && ((offset >= 0x10 && offset < 0x34) ||
+			   (offset >= 0x38 && offset < 0x3c))) {
 		debug("Writing to cfgcache only\n");
 		data = pcie->cfgcache[(offset - 0x10) / 4];
 		data = pci_conv_size_to_32(data, value, offset, size);
@@ -270,12 +268,6 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
 		    (offset & ~3) == PCI_ROM_ADDRESS1)
 			data = 0x0;
 		pcie->cfgcache[(offset - 0x10) / 4] = data;
-		/* mvebu has its own way how to set PCI primary bus number */
-		if (offset == PCI_PRIMARY_BUS) {
-			pcie->first_busno = data & 0xff;
-			debug("Primary bus number was changed to %d\n",
-			      pcie->first_busno);
-		}
 		/* mvebu has its own way how to set PCI secondary bus number */
 		if (offset == PCI_SECONDARY_BUS ||
 		    (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8)) {
@@ -288,10 +280,10 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
 	}
 
 	/*
-	 * PCI bridge is device 0 at primary bus but mvebu has it mapped on
-	 * secondary bus with device number 1.
+	 * PCI bridge is device 0 at the root bus (zero) but mvebu has it
+	 * mapped on secondary bus with device number 1.
 	 */
-	if (busno == pcie->first_busno)
+	if (busno == 0)
 		addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset);
 	else
 		addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
@@ -473,9 +465,9 @@ static int mvebu_pcie_probe(struct udevice *dev)
 	 * target device equals local device number then request is routed to
 	 * PCI Bridge which represent local PCIe Root Port.
 	 *
-	 * It means that PCI primary and secondary buses shares one bus number
+	 * It means that PCI root and secondary buses shares one bus number
 	 * which is configured via local bus number. Determination if config
-	 * request should go to primary or secondary bus is done based on local
+	 * request should go to root or secondary bus is done based on local
 	 * device number.
 	 *
 	 * PCIe is point-to-point bus, so at secondary bus is always exactly one
@@ -487,13 +479,13 @@ static int mvebu_pcie_probe(struct udevice *dev)
 	 * secondary bus number. Set it to 0 as U-Boot CONFIG_PCI_PNP code will
 	 * later configure it via config write requests to the correct value.
 	 * mvebu_pcie_write_config() catches config write requests which tries
-	 * to change primary/secondary bus number and correctly updates local
-	 * bus number based on new secondary bus number.
+	 * to change secondary bus number and correctly updates local bus number
+	 * based on new secondary bus number.
 	 *
 	 * With this configuration is PCI Bridge available at secondary bus as
-	 * device number 1. But it must be available at primary bus as device
+	 * device number 1. But it must be available at root bus (zero) as device
 	 * number 0. So in mvebu_pcie_read_config() and mvebu_pcie_write_config()
-	 * functions rewrite address to the real one when accessing primary bus.
+	 * functions rewrite address to the real one when accessing the root bus.
 	 */
 	mvebu_pcie_set_local_bus_nr(pcie, 0);
 	mvebu_pcie_set_local_dev_nr(pcie, 1);
diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
index 7cde59b8e2..c490dc69c6 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -937,7 +937,7 @@ void comphy_dedicated_phys_init(void)
 		 */
 		if (usb32 == 0) {
 			node = fdt_node_offset_by_compatible(
-				blob, -1, "marvell,armada3700-ehci");
+				blob, -1, "marvell,armada-3700-ehci");
 		} else {
 			node = fdt_node_offset_by_compatible(
 				blob, -1, "marvell,armada3700-xhci");
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index 5bb994fe42..df2460dbd7 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -96,7 +96,7 @@ static int comphy_probe(struct udevice *dev)
 	if (IS_ERR(chip_cfg->hpipe3_base_addr))
 		return PTR_ERR(chip_cfg->hpipe3_base_addr);
 
-	if (device_is_compatible(dev, "marvell,comphy-armada-3700")) {
+	if (device_is_compatible(dev, "marvell,comphy-a3700")) {
 		chip_cfg->comphy_init_map = comphy_a3700_init_serdes_map;
 		chip_cfg->ptr_comphy_chip_init = comphy_a3700_init;
 		chip_cfg->rx_training = NULL;
@@ -145,6 +145,7 @@ static int comphy_probe(struct udevice *dev)
 
 static const struct udevice_id comphy_ids[] = {
 	{ .compatible = "marvell,mvebu-comphy" },
+	{ .compatible = "marvell,comphy-a3700" },
 	{ }
 };
 
diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c
index 1963565c5e..40ca66bdce 100644
--- a/drivers/rtc/ds1307.c
+++ b/drivers/rtc/ds1307.c
@@ -358,6 +358,7 @@ static const struct udevice_id ds1307_rtc_ids[] = {
 	{ .compatible = "dallas,ds1337", .data = ds_1337 },
 	{ .compatible = "dallas,ds1339", .data = ds_1339 },
 	{ .compatible = "dallas,ds1340", .data = ds_1340 },
+	{ .compatible = "microchip,mcp7940x", .data = mcp794xx },
 	{ .compatible = "microchip,mcp7941x", .data = mcp794xx },
 	{ .compatible = "st,m41t11", .data = m41t11 },
 	{ }
diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index 5420bb9772..b7e60c690a 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -123,7 +123,7 @@ static int ehci_mvebu_probe(struct udevice *dev)
 	 * Also, the address decoder doesn't need to get setup with this
 	 * SoC, so don't call usb_brg_adrdec_setup().
 	 */
-	if (device_is_compatible(dev, "marvell,armada3700-ehci"))
+	if (device_is_compatible(dev, "marvell,armada-3700-ehci"))
 		marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup;
 	else
 		usb_brg_adrdec_setup((void *)priv->hcd_base);
@@ -142,7 +142,7 @@ static int ehci_mvebu_probe(struct udevice *dev)
 
 static const struct udevice_id ehci_usb_ids[] = {
 	{ .compatible = "marvell,orion-ehci", },
-	{ .compatible = "marvell,armada3700-ehci", },
+	{ .compatible = "marvell,armada-3700-ehci", },
 	{ }
 };
 
diff --git a/drivers/watchdog/armada-37xx-wdt.c b/drivers/watchdog/armada-37xx-wdt.c
index 6b5e1ab6fc..2e119b9b5a 100644
--- a/drivers/watchdog/armada-37xx-wdt.c
+++ b/drivers/watchdog/armada-37xx-wdt.c
@@ -155,12 +155,9 @@ static int a37xx_wdt_probe(struct udevice *dev)
 	struct a37xx_wdt *priv = dev_get_priv(dev);
 	fdt_addr_t addr;
 
-	addr = dev_read_addr_index(dev, 0);
-	if (addr == FDT_ADDR_T_NONE)
-		goto err;
-	priv->sel_reg = (void __iomem *)addr;
+	priv->sel_reg = (void __iomem *)MVEBU_REGISTER(0x0d064);
 
-	addr = dev_read_addr_index(dev, 1);
+	addr = dev_read_addr(dev);
 	if (addr == FDT_ADDR_T_NONE)
 		goto err;
 	priv->reg = (void __iomem *)addr;