diff options
| author | Dylan Hung <dylan_hung@aspeedtech.com> | 2022-11-11 10:30:08 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-11-25 00:26:01 +0300 |
| commit | 8c7b55724c6f9deb6d8a291cba7f932373313b57 (patch) | |
| tree | ce37283f9407c36727a8335c487451a26b500ef8 /drivers | |
| parent | bd1e1954216a54b1916e932512ee37c7d6a22e58 (diff) | |
| download | u-boot-8c7b55724c6f9deb6d8a291cba7f932373313b57.tar.xz | |
ram: ast2600: Align the RL and WL setting
Use macro to represent the RL and WL setting to ensure the PHY and
controller setting are aligned.
Review-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ram/aspeed/sdram_ast2600.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c index bda02d0629..5d426088be 100644 --- a/drivers/ram/aspeed/sdram_ast2600.c +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -15,6 +15,7 @@ #include <asm/global_data.h> #include <linux/err.h> #include <linux/kernel.h> +#include <linux/bitfield.h> #include <dt-bindings/clock/ast2600-clock.h> #define DDR_PHY_TBL_CHG_ADDR 0xaeeddeea @@ -935,6 +936,7 @@ static void ast2600_sdrammc_lock(struct dram_info *info) static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) { int i; + u32 reg; writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); @@ -969,6 +971,13 @@ static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) writel(ddr4_ac_timing[i], ®s->ac_timing[i]); + /* update CL and WL */ + reg = readl(®s->ac_timing[1]); + reg &= ~(SDRAM_WL_SETTING | SDRAM_CL_SETTING); + reg |= FIELD_PREP(SDRAM_WL_SETTING, CONFIG_WL - 5) | + FIELD_PREP(SDRAM_CL_SETTING, CONFIG_RL - 5); + writel(reg, ®s->ac_timing[1]); + writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); |