Merge tag 'u-boot-rockchip-20220418' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

- Add rk3066 SoC support;
- Add rk3066 MK808 board support;
- dts sync from kernel for rk322x, rk3288;
- some other board level config update;

19 files changed, 1824 insertions, 51 deletions

diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c
index e0cbab6aa0..760f8fe628 100644
--- a/drivers/adc/rockchip-saradc.c
+++ b/drivers/adc/rockchip-saradc.c
@@ -13,6 +13,7 @@
 #include <asm/io.h>
 #include <linux/bitops.h>
 #include <linux/err.h>
+#include <power/regulator.h>
 
 #define SARADC_CTRL_CHN_MASK		GENMASK(2, 0)
 #define SARADC_CTRL_POWER_CTRL		BIT(3)
@@ -100,8 +101,11 @@ int rockchip_saradc_stop(struct udevice *dev)
 
 int rockchip_saradc_probe(struct udevice *dev)
 {
+	struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
 	struct rockchip_saradc_priv *priv = dev_get_priv(dev);
+	struct udevice *vref;
 	struct clk clk;
+	int vref_uv;
 	int ret;
 
 	ret = clk_get_by_index(dev, 0, &clk);
@@ -114,6 +118,23 @@ int rockchip_saradc_probe(struct udevice *dev)
 
 	priv->active_channel = -1;
 
+	ret = device_get_supply_regulator(dev, "vref-supply", &vref);
+	if (ret) {
+		printf("can't get vref-supply: %d\n", ret);
+		return ret;
+	}
+
+	vref_uv = regulator_get_value(vref);
+	if (vref_uv < 0) {
+		printf("can't get vref-supply value: %d\n", vref_uv);
+		return vref_uv;
+	}
+
+	/* VDD supplied by common vref pin */
+	uc_pdata->vdd_supply = vref;
+	uc_pdata->vdd_microvolts = vref_uv;
+	uc_pdata->vss_microvolts = 0;
+
 	return 0;
 }
 
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 913f611a0f..a72d8fe58a 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -6,6 +6,7 @@
 obj-y += clk_pll.o
 obj-$(CONFIG_ROCKCHIP_PX30) += clk_px30.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
+obj-$(CONFIG_ROCKCHIP_RK3066) += clk_rk3066.o
 obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o
diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
index ea874e3f4b..5d467447a1 100644
--- a/drivers/clk/rockchip/clk_px30.c
+++ b/drivers/clk/rockchip/clk_px30.c
@@ -1403,10 +1403,13 @@ static int px30_clk_enable(struct clk *clk)
 {
 	switch (clk->id) {
 	case HCLK_HOST:
+	case HCLK_OTG:
+	case HCLK_SFC:
 	case SCLK_GMAC:
 	case SCLK_GMAC_RX_TX:
 	case SCLK_MAC_REF:
 	case SCLK_MAC_REFOUT:
+	case SCLK_SFC:
 	case ACLK_GMAC:
 	case PCLK_GMAC:
 	case SCLK_GMAC_RMII:
diff --git a/drivers/clk/rockchip/clk_rk3066.c b/drivers/clk/rockchip/clk_rk3066.c
new file mode 100644
index 0000000000..2c12f6e044
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3066.c
@@ -0,0 +1,717 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2015 Google, Inc
+ * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
+ */
+
+#include <bitfield.h>
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dt-structs.h>
+#include <errno.h>
+#include <log.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3066.h>
+#include <asm/arch-rockchip/grf_rk3066.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <dt-bindings/clock/rk3066a-cru.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/log2.h>
+#include <linux/stringify.h>
+
+struct rk3066_clk_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_rockchip_rk3066a_cru dtd;
+#endif
+};
+
+struct pll_div {
+	u32 nr;
+	u32 nf;
+	u32 no;
+};
+
+enum {
+	VCO_MAX_HZ	= 1416U * 1000000,
+	VCO_MIN_HZ	= 300 * 1000000,
+	OUTPUT_MAX_HZ	= 1416U * 1000000,
+	OUTPUT_MIN_HZ	= 30 * 1000000,
+	FREF_MAX_HZ	= 1416U * 1000000,
+	FREF_MIN_HZ	= 30 * 1000,
+};
+
+enum {
+	/* PLL CON0 */
+	PLL_OD_MASK		= GENMASK(3, 0),
+
+	/* PLL CON1 */
+	PLL_NF_MASK		= GENMASK(12, 0),
+
+	/* PLL CON2 */
+	PLL_BWADJ_MASK		= GENMASK(11, 0),
+
+	/* PLL CON3 */
+	PLL_RESET_SHIFT		= 5,
+
+	/* GRF_SOC_STATUS0 */
+	SOCSTS_DPLL_LOCK	= BIT(4),
+	SOCSTS_APLL_LOCK	= BIT(5),
+	SOCSTS_CPLL_LOCK	= BIT(6),
+	SOCSTS_GPLL_LOCK	= BIT(7),
+};
+
+#define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))
+
+#define PLL_DIVISORS(hz, _nr, _no) {\
+	.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
+	_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
+		       (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
+		       "divisors on line " __stringify(__LINE__))
+
+/* Keep divisors as low as possible to reduce jitter and power usage. */
+static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
+static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
+
+static int rk3066_clk_set_pll(struct rk3066_cru *cru, enum rk_clk_id clk_id,
+			      const struct pll_div *div)
+{
+	int pll_id = rk_pll_id(clk_id);
+	struct rk3066_pll *pll = &cru->pll[pll_id];
+	/* All PLLs have the same VCO and output frequency range restrictions. */
+	uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
+	uint output_hz = vco_hz / div->no;
+
+	debug("%s: PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", __func__,
+	      (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
+	assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
+	       output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
+	       (div->no == 1 || !(div->no % 2)));
+
+	/* Enter reset. */
+	rk_setreg(&pll->con3, BIT(PLL_RESET_SHIFT));
+
+	rk_clrsetreg(&pll->con0,
+		     CLKR_MASK | PLL_OD_MASK,
+		     ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
+	rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
+
+	rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
+
+	/* Exit reset. */
+	rk_clrreg(&pll->con3, BIT(PLL_RESET_SHIFT));
+
+	return 0;
+}
+
+static int rk3066_clk_configure_ddr(struct rk3066_cru *cru, struct rk3066_grf *grf,
+				    unsigned int hz)
+{
+	static const struct pll_div dpll_cfg[] = {
+		{.nf = 25, .nr = 2, .no = 1},
+		{.nf = 400, .nr = 9, .no = 2},
+		{.nf = 500, .nr = 9, .no = 2},
+		{.nf = 100, .nr = 3, .no = 1},
+	};
+	int cfg;
+
+	switch (hz) {
+	case 300000000:
+		cfg = 0;
+		break;
+	case 533000000:	/* actually 533.3P MHz */
+		cfg = 1;
+		break;
+	case 666000000:	/* actually 666.6P MHz */
+		cfg = 2;
+		break;
+	case 800000000:
+		cfg = 3;
+		break;
+	default:
+		debug("%s: unsupported SDRAM frequency", __func__);
+		return -EINVAL;
+	}
+
+	/* Enter PLL slow mode. */
+	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
+		     PLL_MODE_SLOW << DPLL_MODE_SHIFT);
+
+	rk3066_clk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
+
+	/* Wait for PLL lock. */
+	while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK))
+		udelay(1);
+
+	/* Enter PLL normal mode. */
+	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
+		     PLL_MODE_NORMAL << DPLL_MODE_SHIFT);
+
+	return 0;
+}
+
+static int rk3066_clk_configure_cpu(struct rk3066_cru *cru, struct rk3066_grf *grf,
+				    unsigned int hz)
+{
+	static const struct pll_div apll_cfg[] = {
+		{.nf = 50, .nr = 1, .no = 2},
+		{.nf = 59, .nr = 1, .no = 1},
+	};
+	int div_core_peri, div_cpu_aclk, cfg;
+
+	/*
+	 * We support two possible frequencies, the safe 600MHz
+	 * which will work with default pmic settings and will
+	 * be set to get away from the 24MHz default and
+	 * the maximum of 1.416Ghz, which boards can set if they
+	 * were able to get pmic support for it.
+	 */
+	switch (hz) {
+	case APLL_SAFE_HZ:
+		cfg = 0;
+		div_core_peri = 1;
+		div_cpu_aclk = 3;
+		break;
+	case APLL_HZ:
+		cfg = 1;
+		div_core_peri = 2;
+		div_cpu_aclk = 3;
+		break;
+	default:
+		debug("unsupported ARMCLK frequency");
+		return -EINVAL;
+	}
+
+	/* Enter PLL slow mode. */
+	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
+		     PLL_MODE_SLOW << APLL_MODE_SHIFT);
+
+	rk3066_clk_set_pll(cru, CLK_ARM, &apll_cfg[cfg]);
+
+	/* Wait for PLL lock. */
+	while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK))
+		udelay(1);
+
+	/* Set divider for peripherals attached to the CPU core. */
+	rk_clrsetreg(&cru->cru_clksel_con[0],
+		     CORE_PERI_DIV_MASK,
+		     div_core_peri << CORE_PERI_DIV_SHIFT);
+
+	/* Set up dependent divisor for cpu_aclk. */
+	rk_clrsetreg(&cru->cru_clksel_con[1],
+		     CPU_ACLK_DIV_MASK,
+		     div_cpu_aclk << CPU_ACLK_DIV_SHIFT);
+
+	/* Enter PLL normal mode. */
+	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
+		     PLL_MODE_NORMAL << APLL_MODE_SHIFT);
+
+	return hz;
+}
+
+static uint32_t rk3066_clk_pll_get_rate(struct rk3066_cru *cru,
+					enum rk_clk_id clk_id)
+{
+	u32 nr, no, nf;
+	u32 con;
+	int pll_id = rk_pll_id(clk_id);
+	struct rk3066_pll *pll = &cru->pll[pll_id];
+	static u8 clk_shift[CLK_COUNT] = {
+		0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
+		GPLL_MODE_SHIFT
+	};
+	uint shift;
+
+	con = readl(&cru->cru_mode_con);
+	shift = clk_shift[clk_id];
+	switch (FIELD_GET(APLL_MODE_MASK, con >> shift)) {
+	case PLL_MODE_SLOW:
+		return OSC_HZ;
+	case PLL_MODE_NORMAL:
+		/* normal mode */
+		con = readl(&pll->con0);
+		no = bitfield_extract_by_mask(con, CLKOD_MASK) + 1;
+		nr = bitfield_extract_by_mask(con, CLKR_MASK) + 1;
+		con = readl(&pll->con1);
+		nf = bitfield_extract_by_mask(con, CLKF_MASK) + 1;
+
+		return (OSC_HZ * nf) / (nr * no);
+	case PLL_MODE_DEEP:
+	default:
+		return 32768;
+	}
+}
+
+static ulong rk3066_clk_mmc_get_clk(struct rk3066_cru *cru, uint gclk_rate,
+				    int periph)
+{
+	uint div;
+	u32 con;
+
+	switch (periph) {
+	case HCLK_EMMC:
+	case SCLK_EMMC:
+		con = readl(&cru->cru_clksel_con[12]);
+		div = bitfield_extract_by_mask(con, EMMC_DIV_MASK);
+		break;
+	case HCLK_SDMMC:
+	case SCLK_SDMMC:
+		con = readl(&cru->cru_clksel_con[11]);
+		div = bitfield_extract_by_mask(con, MMC0_DIV_MASK);
+		break;
+	case HCLK_SDIO:
+	case SCLK_SDIO:
+		con = readl(&cru->cru_clksel_con[12]);
+		div = bitfield_extract_by_mask(con, SDIO_DIV_MASK);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return DIV_TO_RATE(gclk_rate, div) / 2;
+}
+
+static ulong rk3066_clk_mmc_set_clk(struct rk3066_cru *cru, uint gclk_rate,
+				    int  periph, uint freq)
+{
+	int src_clk_div;
+
+	debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
+	/* MMC clock by default divides by 2 internally, so need to provide double in CRU. */
+	src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1;
+	assert(src_clk_div <= 0x3f);
+
+	switch (periph) {
+	case HCLK_EMMC:
+	case SCLK_EMMC:
+		rk_clrsetreg(&cru->cru_clksel_con[12],
+			     EMMC_DIV_MASK,
+			     src_clk_div << EMMC_DIV_SHIFT);
+		break;
+	case HCLK_SDMMC:
+	case SCLK_SDMMC:
+		rk_clrsetreg(&cru->cru_clksel_con[11],
+			     MMC0_DIV_MASK,
+			     src_clk_div << MMC0_DIV_SHIFT);
+		break;
+	case HCLK_SDIO:
+	case SCLK_SDIO:
+		rk_clrsetreg(&cru->cru_clksel_con[12],
+			     SDIO_DIV_MASK,
+			     src_clk_div << SDIO_DIV_SHIFT);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return rk3066_clk_mmc_get_clk(cru, gclk_rate, periph);
+}
+
+static ulong rk3066_clk_spi_get_clk(struct rk3066_cru *cru, uint gclk_rate,
+				    int periph)
+{
+	uint div;
+	u32 con;
+
+	switch (periph) {
+	case SCLK_SPI0:
+		con = readl(&cru->cru_clksel_con[25]);
+		div = bitfield_extract_by_mask(con, SPI0_DIV_MASK);
+		break;
+	case SCLK_SPI1:
+		con = readl(&cru->cru_clksel_con[25]);
+		div = bitfield_extract_by_mask(con, SPI1_DIV_MASK);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return DIV_TO_RATE(gclk_rate, div);
+}
+
+static ulong rk3066_clk_spi_set_clk(struct rk3066_cru *cru, uint gclk_rate,
+				    int periph, uint freq)
+{
+	int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
+
+	assert(src_clk_div < 128);
+	switch (periph) {
+	case SCLK_SPI0:
+		assert(src_clk_div <= SPI0_DIV_MASK >> SPI0_DIV_SHIFT);
+		rk_clrsetreg(&cru->cru_clksel_con[25],
+			     SPI0_DIV_MASK,
+			     src_clk_div << SPI0_DIV_SHIFT);
+		break;
+	case SCLK_SPI1:
+		assert(src_clk_div <= SPI1_DIV_MASK >> SPI1_DIV_SHIFT);
+		rk_clrsetreg(&cru->cru_clksel_con[25],
+			     SPI1_DIV_MASK,
+			     src_clk_div << SPI1_DIV_SHIFT);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return rk3066_clk_spi_get_clk(cru, gclk_rate, periph);
+}
+
+static ulong rk3066_clk_saradc_get_clk(struct rk3066_cru *cru, int periph)
+{
+	u32 div, con;
+
+	switch (periph) {
+	case SCLK_SARADC:
+		con = readl(&cru->cru_clksel_con[24]);
+		div = bitfield_extract_by_mask(con, SARADC_DIV_MASK);
+		break;
+	case SCLK_TSADC:
+		con = readl(&cru->cru_clksel_con[34]);
+		div = bitfield_extract_by_mask(con, TSADC_DIV_MASK);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return DIV_TO_RATE(PERI_PCLK_HZ, div);
+}
+
+static ulong rk3066_clk_saradc_set_clk(struct rk3066_cru *cru, uint hz,
+				       int periph)
+{
+	int src_clk_div;
+
+	src_clk_div = DIV_ROUND_UP(PERI_PCLK_HZ, hz) - 1;
+	assert(src_clk_div < 128);
+
+	switch (periph) {
+	case SCLK_SARADC:
+		rk_clrsetreg(&cru->cru_clksel_con[24],
+			     SARADC_DIV_MASK,
+			     src_clk_div << SARADC_DIV_SHIFT);
+		break;
+	case SCLK_TSADC:
+		rk_clrsetreg(&cru->cru_clksel_con[34],
+			     SARADC_DIV_MASK,
+			     src_clk_div << SARADC_DIV_SHIFT);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return rk3066_clk_saradc_get_clk(cru, periph);
+}
+
+static void rk3066_clk_init(struct rk3066_cru *cru, struct rk3066_grf *grf)
+{
+	u32 aclk_div, hclk_div, pclk_div, h2p_div;
+
+	/* Enter PLL slow mode. */
+	rk_clrsetreg(&cru->cru_mode_con,
+		     GPLL_MODE_MASK |
+		     CPLL_MODE_MASK,
+		     PLL_MODE_SLOW << GPLL_MODE_SHIFT |
+		     PLL_MODE_SLOW << CPLL_MODE_SHIFT);
+
+	/* Init PLL. */
+	rk3066_clk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
+	rk3066_clk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
+
+	/* Wait for PLL lock. */
+	while ((readl(&grf->soc_status0) &
+		(SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
+	       (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
+		udelay(1);
+
+	/*
+	 * Select CPU clock PLL source and
+	 * reparent aclk_cpu_pre from APPL to GPLL.
+	 * Set up dependent divisors for PCLK/HCLK and ACLK clocks.
+	 */
+	aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1;
+	assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
+
+	rk_clrsetreg(&cru->cru_clksel_con[0],
+		     CPU_ACLK_PLL_MASK |
+		     A9_CORE_DIV_MASK,
+		     CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT |
+		     aclk_div << A9_CORE_DIV_SHIFT);
+
+	hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ);
+	assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3);
+	pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ);
+	assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4);
+	h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ);
+	assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3);
+
+	rk_clrsetreg(&cru->cru_clksel_con[1],
+		     AHB2APB_DIV_MASK |
+		     CPU_PCLK_DIV_MASK |
+		     CPU_HCLK_DIV_MASK,
+		     h2p_div << AHB2APB_DIV_SHIFT |
+		     pclk_div << CPU_PCLK_DIV_SHIFT |
+		     hclk_div << CPU_HCLK_DIV_SHIFT);
+
+	/*
+	 * Select PERI clock PLL source and
+	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+	 */
+	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
+	assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
+
+	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
+	assert((1 << hclk_div) * PERI_HCLK_HZ ==
+	       PERI_ACLK_HZ && (hclk_div < 0x4));
+
+	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
+	assert((1 << pclk_div) * PERI_PCLK_HZ ==
+	       PERI_ACLK_HZ && (pclk_div < 0x4));
+
+	rk_clrsetreg(&cru->cru_clksel_con[10],
+		     PERI_PCLK_DIV_MASK |
+		     PERI_HCLK_DIV_MASK |
+		     PERI_ACLK_DIV_MASK,
+		     PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
+		     pclk_div << PERI_PCLK_DIV_SHIFT |
+		     hclk_div << PERI_HCLK_DIV_SHIFT |
+		     aclk_div << PERI_ACLK_DIV_SHIFT);
+
+	/* Enter PLL normal mode. */
+	rk_clrsetreg(&cru->cru_mode_con,
+		     GPLL_MODE_MASK |
+		     CPLL_MODE_MASK,
+		     PLL_MODE_NORMAL << GPLL_MODE_SHIFT |
+		     PLL_MODE_NORMAL << CPLL_MODE_SHIFT);
+
+	rk3066_clk_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000);
+}
+
+static ulong rk3066_clk_get_rate(struct clk *clk)
+{
+	struct rk3066_clk_priv *priv = dev_get_priv(clk->dev);
+	ulong new_rate, gclk_rate;
+
+	gclk_rate = rk3066_clk_pll_get_rate(priv->cru, CLK_GENERAL);
+	switch (clk->id) {
+	case 1 ... 4:
+		new_rate = rk3066_clk_pll_get_rate(priv->cru, clk->id);
+		break;
+	case HCLK_EMMC:
+	case HCLK_SDMMC:
+	case HCLK_SDIO:
+	case SCLK_EMMC:
+	case SCLK_SDMMC:
+	case SCLK_SDIO:
+		new_rate = rk3066_clk_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
+						  clk->id);
+		break;
+	case SCLK_SPI0:
+	case SCLK_SPI1:
+		new_rate = rk3066_clk_spi_get_clk(priv->cru, PERI_PCLK_HZ,
+						  clk->id);
+		break;
+	case PCLK_I2C0:
+	case PCLK_I2C1:
+	case PCLK_I2C2:
+	case PCLK_I2C3:
+	case PCLK_I2C4:
+		return gclk_rate;
+	case SCLK_SARADC:
+	case SCLK_TSADC:
+		new_rate = rk3066_clk_saradc_get_clk(priv->cru, clk->id);
+		break;
+	case SCLK_TIMER0:
+	case SCLK_TIMER1:
+	case SCLK_TIMER2:
+	case SCLK_UART0:
+	case SCLK_UART1:
+	case SCLK_UART2:
+	case SCLK_UART3:
+		return OSC_HZ;
+	default:
+		return -ENOENT;
+	}
+
+	return new_rate;
+}
+
+static ulong rk3066_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct rk3066_clk_priv *priv = dev_get_priv(clk->dev);
+	struct rk3066_cru *cru = priv->cru;
+	ulong new_rate;
+
+	switch (clk->id) {
+	case PLL_APLL:
+		new_rate = rk3066_clk_configure_cpu(priv->cru, priv->grf, rate);
+		break;
+	case CLK_DDR:
+		new_rate = rk3066_clk_configure_ddr(priv->cru, priv->grf, rate);
+		break;
+	case HCLK_EMMC:
+	case HCLK_SDMMC:
+	case HCLK_SDIO:
+	case SCLK_EMMC:
+	case SCLK_SDMMC:
+	case SCLK_SDIO:
+		new_rate = rk3066_clk_mmc_set_clk(cru, PERI_HCLK_HZ,
+						  clk->id, rate);
+		break;
+	case SCLK_SPI0:
+	case SCLK_SPI1:
+		new_rate = rk3066_clk_spi_set_clk(cru, PERI_PCLK_HZ,
+						  clk->id, rate);
+		break;
+	case SCLK_SARADC:
+	case SCLK_TSADC:
+		new_rate = rk3066_clk_saradc_set_clk(cru, rate, clk->id);
+		break;
+	case PLL_CPLL:
+	case PLL_GPLL:
+	case ACLK_CPU:
+	case HCLK_CPU:
+	case PCLK_CPU:
+	case ACLK_PERI:
+	case HCLK_PERI:
+	case PCLK_PERI:
+		return 0;
+	default:
+		return -ENOENT;
+	}
+
+	return new_rate;
+}
+
+static int rk3066_clk_enable(struct clk *clk)
+{
+	struct rk3066_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case HCLK_NANDC0:
+		rk_clrreg(&priv->cru->cru_clkgate_con[5], BIT(9));
+		break;
+	case HCLK_SDMMC:
+		rk_clrreg(&priv->cru->cru_clkgate_con[5], BIT(10));
+		break;
+	case HCLK_SDIO:
+		rk_clrreg(&priv->cru->cru_clkgate_con[5], BIT(11));
+		break;
+	}
+
+	return 0;
+}
+
+static int rk3066_clk_disable(struct clk *clk)
+{
+	struct rk3066_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case HCLK_NANDC0:
+		rk_setreg(&priv->cru->cru_clkgate_con[5], BIT(9));
+		break;
+	case HCLK_SDMMC:
+		rk_setreg(&priv->cru->cru_clkgate_con[5], BIT(10));
+		break;
+	case HCLK_SDIO:
+		rk_setreg(&priv->cru->cru_clkgate_con[5], BIT(11));
+		break;
+	}
+
+	return 0;
+}
+
+static struct clk_ops rk3066_clk_ops = {
+	.disable	= rk3066_clk_disable,
+	.enable	= rk3066_clk_enable,
+	.get_rate	= rk3066_clk_get_rate,
+	.set_rate	= rk3066_clk_set_rate,
+};
+
+static int rk3066_clk_of_to_plat(struct udevice *dev)
+{
+	if (CONFIG_IS_ENABLED(OF_REAL)) {
+		struct rk3066_clk_priv *priv = dev_get_priv(dev);
+
+		priv->cru = dev_read_addr_ptr(dev);
+	}
+
+	return 0;
+}
+
+static int rk3066_clk_probe(struct udevice *dev)
+{
+	struct rk3066_clk_priv *priv = dev_get_priv(dev);
+
+	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	if (IS_ERR(priv->grf))
+		return PTR_ERR(priv->grf);
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct rk3066_clk_plat *plat = dev_get_plat(dev);
+
+	priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
+#endif
+
+	if (IS_ENABLED(CONFIG_TPL_BUILD)) {
+		rk3066_clk_init(priv->cru, priv->grf);
+
+		/* Init CPU frequency. */
+		rk3066_clk_configure_cpu(priv->cru, priv->grf, APLL_SAFE_HZ);
+	}
+
+	return 0;
+}
+
+static int rk3066_clk_bind(struct udevice *dev)
+{
+	struct udevice *sys_child;
+	struct sysreset_reg *priv;
+	int reg_offset, ret;
+
+	/* The reset driver does not have a device node, so bind it here. */
+	ret = device_bind(dev, DM_DRIVER_GET(sysreset_rockchip), "sysreset",
+			  NULL, ofnode_null(), &sys_child);
+	if (ret) {
+		dev_dbg(dev, "Warning: No sysreset driver: ret=%d\n", ret);
+	} else {
+		priv = malloc(sizeof(struct sysreset_reg));
+		priv->glb_srst_fst_value = offsetof(struct rk3066_cru,
+						    cru_glb_srst_fst_value);
+		priv->glb_srst_snd_value = offsetof(struct rk3066_cru,
+						    cru_glb_srst_snd_value);
+		dev_set_priv(sys_child, priv);
+	}
+
+	if (CONFIG_IS_ENABLED(RESET_ROCKCHIP)) {
+		reg_offset = offsetof(struct rk3066_cru, cru_softrst_con[0]);
+		ret = rockchip_reset_bind(dev, reg_offset, 9);
+		if (ret)
+			dev_dbg(dev, "Warning: software reset driver bind failed\n");
+	}
+
+	return 0;
+}
+
+static const struct udevice_id rk3066_clk_ids[] = {
+	{ .compatible = "rockchip,rk3066a-cru" },
+	{ }
+};
+
+U_BOOT_DRIVER(rockchip_rk3066a_cru) = {
+	.name		= "rockchip_rk3066a_cru",
+	.id		= UCLASS_CLK,
+	.ops		= &rk3066_clk_ops,
+	.probe		= rk3066_clk_probe,
+	.bind		= rk3066_clk_bind,
+	.of_match	= rk3066_clk_ids,
+	.of_to_plat	= rk3066_clk_of_to_plat,
+	.priv_auto	= sizeof(struct rk3066_clk_priv),
+	.plat_auto	= sizeof(struct rk3066_clk_plat),
+};
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 7f8dea1e34..573bf16c87 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -119,15 +119,15 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 	host->priv = dev;
 	host->dev_index = 0;
 	priv->fifo_depth = dtplat->fifo_depth;
-	priv->fifo_mode = 0;
+	priv->fifo_mode = dtplat->u_boot_spl_fifo_mode;
 	priv->minmax[0] = 400000;  /*  400 kHz */
 	priv->minmax[1] = dtplat->max_frequency;
 
-	ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk);
+	ret = clk_get_by_phandle(dev, &dtplat->clocks[1], &priv->clk);
 	if (ret < 0)
 		return ret;
 #else
-	ret = clk_get_by_index(dev, 0, &priv->clk);
+	ret = clk_get_by_index(dev, 1, &priv->clk);
 	if (ret < 0)
 		return ret;
 #endif
@@ -180,5 +180,6 @@ U_BOOT_DRIVER(rockchip_rk3288_dw_mshc) = {
 	.plat_auto	= sizeof(struct rockchip_mmc_plat),
 };
 
+DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk2928_dw_mshc)
 DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3328_dw_mshc)
 DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3368_dw_mshc)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 1fdc841517..9608770d4e 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -227,7 +227,7 @@ static int rk3399_emmc_get_phy(struct udevice *dev)
 	}
 
 	grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-	if (grf_base < 0) {
+	if (IS_ERR_OR_NULL(grf_base)) {
 		printf("%s Get syscon grf failed", __func__);
 		return -ENODEV;
 	}
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index fcf19f877a..7d03f8101d 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -5,6 +5,7 @@
 obj-y += pinctrl-rockchip-core.o
 obj-$(CONFIG_ROCKCHIP_PX30) += pinctrl-px30.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += pinctrl-rk3036.o
+obj-$(CONFIG_ROCKCHIP_RK3066) += pinctrl-rk3066.o
 obj-$(CONFIG_ROCKCHIP_RK3128) += pinctrl-rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) += pinctrl-rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += pinctrl-rk322x.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3066.c b/drivers/pinctrl/rockchip/pinctrl-rk3066.c
new file mode 100644
index 0000000000..598b63223e
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3066.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+
+#include "pinctrl-rockchip.h"
+
+static int rk3066_pinctrl_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int iomux_num = (pin / 8);
+	struct regmap *regmap;
+	int reg, ret, mask, mux_type;
+	u8 bit;
+	u32 data;
+
+	regmap = priv->regmap_base;
+
+	/* get basic quadrupel of mux registers and the correct reg inside */
+	mux_type = bank->iomux[iomux_num].type;
+	reg = bank->iomux[iomux_num].offset;
+	reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+	data = (mask << (bit + 16));
+	data |= (mux & mask) << bit;
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
+#define RK3066_PULL_OFFSET		0x118
+#define RK3066_PULL_PINS_PER_REG	16
+#define RK3066_PULL_BANK_STRIDE		8
+
+static void rk3066_pinctrl_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+						 int pin_num, struct regmap **regmap,
+						 int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+
+	*regmap = priv->regmap_base;
+	*reg = RK3066_PULL_OFFSET;
+	*reg += bank->bank_num * RK3066_PULL_BANK_STRIDE;
+	*reg += (pin_num / RK3066_PULL_PINS_PER_REG) * 4;
+
+	*bit = pin_num % RK3066_PULL_PINS_PER_REG;
+};
+
+static int rk3066_pinctrl_set_pull(struct rockchip_pin_bank *bank,
+				   int pin_num, int pull)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u8 bit;
+	u32 data;
+
+	if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
+	    pull != PIN_CONFIG_BIAS_DISABLE)
+		return -EOPNOTSUPP;
+
+	rk3066_pinctrl_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	data = BIT(bit + 16);
+	if (pull == PIN_CONFIG_BIAS_DISABLE)
+		data |= BIT(bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
+}
+
+static struct rockchip_pin_bank rk3066_pin_banks[] = {
+	PIN_BANK(0, 32, "gpio0"),
+	PIN_BANK(1, 32, "gpio1"),
+	PIN_BANK(2, 32, "gpio2"),
+	PIN_BANK(3, 32, "gpio3"),
+	PIN_BANK(4, 32, "gpio4"),
+	PIN_BANK(6, 16, "gpio6"),
+};
+
+static struct rockchip_pin_ctrl rk3066_pin_ctrl = {
+	.pin_banks		= rk3066_pin_banks,
+	.nr_banks		= ARRAY_SIZE(rk3066_pin_banks),
+	.grf_mux_offset		= 0xa8,
+	.set_mux		= rk3066_pinctrl_set_mux,
+	.set_pull		= rk3066_pinctrl_set_pull,
+};
+
+static const struct udevice_id rk3066_pinctrl_ids[] = {
+	{
+		.compatible = "rockchip,rk3066a-pinctrl",
+		.data = (ulong)&rk3066_pin_ctrl
+	},
+	{}
+};
+
+U_BOOT_DRIVER(rockchip_rk3066a_pinctrl) = {
+	.name		= "rockchip_rk3066a_pinctrl",
+	.id		= UCLASS_PINCTRL,
+	.ops		= &rockchip_pinctrl_ops,
+	.probe		= rockchip_pinctrl_probe,
+#if CONFIG_IS_ENABLED(OF_REAL)
+	.bind		= dm_scan_fdt_dev,
+#endif
+	.of_match	= rk3066_pinctrl_ids,
+	.priv_auto	= sizeof(struct rockchip_pinctrl_priv),
+};
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index ca1c289b88..6d530c29af 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -5,6 +5,7 @@
 
 obj-$(CONFIG_ROCKCHIP_PX30) += sdram_px30.o sdram_pctl_px30.o sdram_phy_px30.o
 obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
+obj-$(CONFIG_ROCKCHIP_RK3066) = sdram_rk3066.o
 obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
diff --git a/drivers/ram/rockchip/sdram_rk3066.c b/drivers/ram/rockchip/sdram_rk3066.c
new file mode 100644
index 0000000000..832154ee3a
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3066.c
@@ -0,0 +1,892 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ *
+ * Adapted from the very similar rk3188 ddr init.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dt-structs.h>
+#include <errno.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <ram.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3066.h>
+#include <asm/arch-rockchip/ddr_rk3188.h>
+#include <asm/arch-rockchip/grf_rk3066.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/pmu_rk3188.h>
+#include <asm/arch-rockchip/sdram_rk3288.h>
+#include <asm/arch-rockchip/sdram.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+struct rk3066_dmc_chan_info {
+	struct rk3288_ddr_pctl *pctl;
+	struct rk3288_ddr_publ *publ;
+	struct rk3188_msch *msch;
+};
+
+struct rk3066_dmc_dram_info {
+	struct rk3066_dmc_chan_info chan[1];
+	struct ram_info info;
+	struct clk ddr_clk;
+	struct rk3066_cru *cru;
+	struct rk3066_grf *grf;
+	struct rk3066_sgrf *sgrf;
+	struct rk3188_pmu *pmu;
+};
+
+struct rk3066_dmc_sdram_params {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_rockchip_rk3066_dmc of_plat;
+#endif
+	struct rk3288_sdram_channel ch[2];
+	struct rk3288_sdram_pctl_timing pctl_timing;
+	struct rk3288_sdram_phy_timing phy_timing;
+	struct rk3288_base_params base;
+	int num_channels;
+	struct regmap *map;
+};
+
+const int rk3066_dmc_ddrconf_table[] = {
+	/*
+	 * [5:4] row(13+n)
+	 * [1:0] col(9+n), assume bw=2
+	 * row	    col,bw
+	 */
+	0,
+	(2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
+	(1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
+	(0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
+	(2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
+	(1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
+	(0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
+	(1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT,
+	(0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+};
+
+#define TEST_PATTERN			0x5aa5f00f
+#define DQS_GATE_TRAINING_ERROR_RANK0	BIT(4)
+#define DQS_GATE_TRAINING_ERROR_RANK1	BIT(5)
+
+static void rk3066_dmc_copy_to_reg(u32 *dest, const u32 *src, u32 n)
+{
+	int i;
+
+	for (i = 0; i < n / sizeof(u32); i++) {
+		writel(*src, dest);
+		src++;
+		dest++;
+	}
+}
+
+static void rk3066_dmc_ddr_reset(struct rk3066_cru *cru, u32 ch, u32 ctl, u32 phy)
+{
+	u32 phy_ctl_srstn_shift = 13;
+	u32 ctl_psrstn_shift = 11;
+	u32 ctl_srstn_shift = 10;
+	u32 phy_psrstn_shift = 9;
+	u32 phy_srstn_shift = 8;
+
+	rk_clrsetreg(&cru->cru_softrst_con[5],
+		     1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
+		     1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
+		     1 << phy_srstn_shift,
+		     phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
+		     ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
+		     phy << phy_srstn_shift);
+}
+
+static void rk3066_dmc_ddr_phy_ctl_reset(struct rk3066_cru *cru, u32 ch, u32 n)
+{
+	u32 phy_ctl_srstn_shift = 13;
+
+	rk_clrsetreg(&cru->cru_softrst_con[5],
+		     1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
+}
+
+static void rk3066_dmc_phy_pctrl_reset(struct rk3066_cru *cru,
+				       struct rk3288_ddr_publ *publ,
+				       int channel)
+{
+	int i;
+
+	rk3066_dmc_ddr_reset(cru, channel, 1, 1);
+	udelay(1);
+	clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
+	for (i = 0; i < 4; i++)
+		clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
+
+	udelay(10);
+	setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
+	for (i = 0; i < 4; i++)
+		setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
+
+	udelay(10);
+	rk3066_dmc_ddr_reset(cru, channel, 1, 0);
+	udelay(10);
+	rk3066_dmc_ddr_reset(cru, channel, 0, 0);
+	udelay(10);
+}
+
+static void rk3066_dmc_phy_dll_bypass_set(struct rk3288_ddr_publ *publ, u32 freq)
+{
+	int i;
+
+	if (freq <= 250000000) {
+		if (freq <= 150000000)
+			clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
+		else
+			setbits_le32(&publ->dllgcr, SBIAS_BYPASS);
+		setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
+		for (i = 0; i < 4; i++)
+			setbits_le32(&publ->datx8[i].dxdllcr,
+				     DXDLLCR_DLLDIS);
+
+		setbits_le32(&publ->pir, PIR_DLLBYP);
+	} else {
+		clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
+		clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
+		for (i = 0; i < 4; i++) {
+			clrbits_le32(&publ->datx8[i].dxdllcr,
+				     DXDLLCR_DLLDIS);
+		}
+
+		clrbits_le32(&publ->pir, PIR_DLLBYP);
+	}
+}
+
+static void rk3066_dmc_dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype)
+{
+	writel(DFI_INIT_START, &pctl->dfistcfg0);
+	writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
+	       &pctl->dfistcfg1);
+	writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
+	writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
+	       &pctl->dfilpcfg0);
+
+	writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay);
+	writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata);
+	writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat);
+	writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis);
+	writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken);
+	writel(1, &pctl->dfitphyupdtype0);
+
+	/* CS0 and CS1 write ODT enable. */
+	writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
+	       &pctl->dfiodtcfg);
+	/* Write ODT length. */
+	writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
+	/* Disable phyupd and ctrlupd. */
+	writel(0, &pctl->dfiupdcfg);
+}
+
+static void rk3066_dmc_ddr_set_ddr3_mode(struct rk3066_grf *grf, uint channel,
+					 bool ddr3_mode)
+{
+	uint mask, val;
+
+	mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT;
+	val = ddr3_mode << MSCH4_MAINDDR3_SHIFT;
+	rk_clrsetreg(&grf->soc_con2, mask, val);
+}
+
+static void rk3066_dmc_ddr_rank_2_row15en(struct rk3066_grf *grf, bool enable)
+{
+	uint mask, val;
+
+	mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT;
+	val = enable << RANK_TO_ROW15_EN_SHIFT;
+	rk_clrsetreg(&grf->soc_con2, mask, val);
+}
+
+static void rk3066_dmc_pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl,
+				struct rk3066_dmc_sdram_params *sdram_params,
+				struct rk3066_grf *grf)
+{
+	rk3066_dmc_copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
+			       sizeof(sdram_params->pctl_timing));
+	switch (sdram_params->base.dramtype) {
+	case DDR3:
+		if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {
+			writel(sdram_params->pctl_timing.tcl - 3,
+			       &pctl->dfitrddataen);
+		} else {
+			writel(sdram_params->pctl_timing.tcl - 2,
+			       &pctl->dfitrddataen);
+		}
+		writel(sdram_params->pctl_timing.tcwl - 1,
+		       &pctl->dfitphywrlat);
+		writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
+		       DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
+		       1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
+		       &pctl->mcfg);
+		rk3066_dmc_ddr_set_ddr3_mode(grf, channel, true);
+		break;
+	}
+
+	setbits_le32(&pctl->scfg, 1);
+}
+
+static void rk3066_dmc_phy_cfg(const struct rk3066_dmc_chan_info *chan, int channel,
+			       struct rk3066_dmc_sdram_params *sdram_params)
+{
+	struct rk3288_ddr_publ *publ = chan->publ;
+	struct rk3188_msch *msch = chan->msch;
+	uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;
+	u32 dinit2;
+	int i;
+
+	dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000);
+	/* Set DDR PHY timing. */
+	rk3066_dmc_copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,
+			       sizeof(sdram_params->phy_timing));
+	writel(sdram_params->base.noc_timing, &msch->ddrtiming);
+	writel(0x3f, &msch->readlatency);
+	writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT |
+	       DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT |
+	       8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]);
+	writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT |
+	       DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT,
+	       &publ->ptr[1]);
+	writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT |
+	       DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT,
+	       &publ->ptr[2]);
+
+	switch (sdram_params->base.dramtype) {
+	case DDR3:
+		clrbits_le32(&publ->pgcr, 0x1f);
+		clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
+				DDRMD_DDR3 << DDRMD_SHIFT);
+		break;
+	}
+	if (sdram_params->base.odt) {
+		/* Enable dynamic RTT. */
+		for (i = 0; i < 4; i++)
+			setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
+	} else {
+		/* Disable dynamic RTT. */
+		for (i = 0; i < 4; i++)
+			clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
+	}
+}
+
+static void rk3066_dmc_phy_init(struct rk3288_ddr_publ *publ)
+{
+	setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST
+		     | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
+	udelay(1);
+	while ((readl(&publ->pgsr) &
+		(PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
+	       (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
+		;
+}
+
+static void rk3066_dmc_send_command(struct rk3288_ddr_pctl *pctl, u32 rank,
+				    u32 cmd, u32 arg)
+{
+	writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
+	udelay(1);
+	while (readl(&pctl->mcmd) & START_CMD)
+		;
+}
+
+static inline void rk3066_dmc_send_command_op(struct rk3288_ddr_pctl *pctl,
+					      u32 rank, u32 cmd, u32 ma, u32 op)
+{
+	rk3066_dmc_send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
+				(op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT);
+}
+
+static void rk3066_dmc_memory_init(struct rk3288_ddr_publ *publ,
+				   u32 dramtype)
+{
+	setbits_le32(&publ->pir,
+		     (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP
+		      | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
+		      | (dramtype == DDR3 ? PIR_DRAMRST : 0)));
+	udelay(1);
+	while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
+	       != (PGSR_IDONE | PGSR_DLDONE))
+		;
+}
+
+static void rk3066_dmc_move_to_config_state(struct rk3288_ddr_publ *publ,
+					    struct rk3288_ddr_pctl *pctl)
+{
+	unsigned int state;
+
+	while (1) {
+		state = readl(&pctl->stat) & PCTL_STAT_MSK;
+
+		switch (state) {
+		case LOW_POWER:
+			writel(WAKEUP_STATE, &pctl->sctl);
+			while ((readl(&pctl->stat) & PCTL_STAT_MSK)
+			       != ACCESS)
+				;
+			/* Wait DLL lock. */
+			while ((readl(&publ->pgsr) & PGSR_DLDONE)
+			       != PGSR_DLDONE)
+				;
+			/*
+			 * If at low power state we need to wakeup first
+			 * and then enter the config.
+			 */
+			fallthrough;
+		case ACCESS:
+			fallthrough;
+		case INIT_MEM:
+			writel(CFG_STATE, &pctl->sctl);
+			while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
+				;
+			break;
+		case CONFIG:
+			return;
+		default:
+			break;
+		}
+	}
+}
+
+static void rk3066_dmc_set_bandwidth_ratio(const struct rk3066_dmc_chan_info *chan, int channel,
+					   u32 n, struct rk3066_grf *grf)
+{
+	struct rk3288_ddr_pctl *pctl = chan->pctl;
+	struct rk3288_ddr_publ *publ = chan->publ;
+	struct rk3188_msch *msch = chan->msch;
+
+	if (n == 1) {
+		setbits_le32(&pctl->ppcfg, 1);
+		setbits_le32(&msch->ddrtiming, 1 << 31);
+		/* Data byte disable. */
+		clrbits_le32(&publ->datx8[2].dxgcr, 1);
+		clrbits_le32(&publ->datx8[3].dxgcr, 1);
+		/* Disable DLL. */
+		setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
+		setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
+	} else {
+		clrbits_le32(&pctl->ppcfg, 1);
+		clrbits_le32(&msch->ddrtiming, 1 << 31);
+		/* Data byte enable.*/
+		setbits_le32(&publ->datx8[2].dxgcr, 1);
+		setbits_le32(&publ->datx8[3].dxgcr, 1);
+
+		/* Enable DLL. */
+		clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
+		clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
+		/* Reset DLL. */
+		clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
+		clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
+		udelay(10);
+		setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
+		setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
+	}
+	setbits_le32(&pctl->dfistcfg0, 1 << 2);
+}
+
+static int rk3066_dmc_data_training(const struct rk3066_dmc_chan_info *chan, int channel,
+				    struct rk3066_dmc_sdram_params *sdram_params)
+{
+	unsigned int j;
+	int ret = 0;
+	u32 rank;
+	int i;
+	u32 step[2] = { PIR_QSTRN, PIR_RVTRN };
+	struct rk3288_ddr_publ *publ = chan->publ;
+	struct rk3288_ddr_pctl *pctl = chan->pctl;
+
+	/* Disable auto refresh. */
+	writel(0, &pctl->trefi);
+
+	if (sdram_params->base.dramtype != LPDDR3)
+		setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
+	rank = sdram_params->ch[channel].rank | 1;
+	for (j = 0; j < ARRAY_SIZE(step); j++) {
+		/*
+		 * Trigger QSTRN and RVTRN.
+		 * Clear DTDONE status.
+		 */
+		setbits_le32(&publ->pir, PIR_CLRSR);
+
+		/* Trigger DTT. */
+		setbits_le32(&publ->pir,
+			     PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP |
+			     PIR_CLRSR);
+		udelay(1);
+		/* Wait echo byte DTDONE. */
+		while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
+		       != rank)
+			;
+		while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
+		       != rank)
+			;
+		if (!(readl(&pctl->ppcfg) & 1)) {
+			while ((readl(&publ->datx8[2].dxgsr[0])
+				& rank) != rank)
+				;
+			while ((readl(&publ->datx8[3].dxgsr[0])
+				& rank) != rank)
+				;
+		}
+		if (readl(&publ->pgsr) &
+		    (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
+			ret = -1;
+			break;
+		}
+	}
+	/* Send some auto refresh to complement the lost while DTT. */
+	for (i = 0; i < (rank > 1 ? 8 : 4); i++)
+		rk3066_dmc_send_command(pctl, rank, REF_CMD, 0);
+
+	if (sdram_params->base.dramtype != LPDDR3)
+		clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
+
+	/* Resume auto refresh. */
+	writel(sdram_params->pctl_timing.trefi, &pctl->trefi);
+
+	return ret;
+}
+
+static void rk3066_dmc_move_to_access_state(const struct rk3066_dmc_chan_info *chan)
+{
+	struct rk3288_ddr_publ *publ = chan->publ;
+	struct rk3288_ddr_pctl *pctl = chan->pctl;
+	unsigned int state;
+
+	while (1) {
+		state = readl(&pctl->stat) & PCTL_STAT_MSK;
+
+		switch (state) {
+		case LOW_POWER:
+			if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
+			     LP_TRIG_MASK) == 1)
+				return;
+
+			writel(WAKEUP_STATE, &pctl->sctl);
+			while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
+				;
+			/* Wait DLL lock. */
+			while ((readl(&publ->pgsr) & PGSR_DLDONE)
+			       != PGSR_DLDONE)
+				;
+			break;
+		case INIT_MEM:
+			writel(CFG_STATE, &pctl->sctl);
+			while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
+				;
+			fallthrough;
+		case CONFIG:
+			writel(GO_STATE, &pctl->sctl);
+			while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
+				;
+			break;
+		case ACCESS:
+			return;
+		default:
+			break;
+		}
+	}
+}
+
+static void rk3066_dmc_dram_cfg_rbc(const struct rk3066_dmc_chan_info *chan, u32 chnum,
+				    struct rk3066_dmc_sdram_params *sdram_params)
+{
+	struct rk3288_ddr_publ *publ = chan->publ;
+
+	if (sdram_params->ch[chnum].bk == 3)
+		clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT,
+				1 << PDQ_SHIFT);
+	else
+		clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT);
+
+	writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
+}
+
+static void rk3066_dmc_dram_all_config(const struct rk3066_dmc_dram_info *dram,
+				       struct rk3066_dmc_sdram_params *sdram_params)
+{
+	unsigned int chan;
+	u32 sys_reg = 0;
+
+	sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
+	sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
+	for (chan = 0; chan < sdram_params->num_channels; chan++) {
+		const struct rk3288_sdram_channel *info =
+				&sdram_params->ch[chan];
+
+		sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
+		sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
+		sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
+		sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
+		sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
+		sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
+		sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
+		sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
+		sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
+
+		rk3066_dmc_dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
+	}
+	if (sdram_params->ch[0].rank == 2)
+		rk3066_dmc_ddr_rank_2_row15en(dram->grf, 0);
+	else
+		rk3066_dmc_ddr_rank_2_row15en(dram->grf, 1);
+
+	writel(sys_reg, &dram->pmu->sys_reg[2]);
+}
+
+static int rk3066_dmc_sdram_rank_bw_detect(struct rk3066_dmc_dram_info *dram, int channel,
+					   struct rk3066_dmc_sdram_params *sdram_params)
+{
+	int reg;
+	int need_trainig = 0;
+	const struct rk3066_dmc_chan_info *chan = &dram->chan[channel];
+	struct rk3288_ddr_publ *publ = chan->publ;
+
+	rk3066_dmc_ddr_rank_2_row15en(dram->grf, 0);
+
+	if (rk3066_dmc_data_training(chan, channel, sdram_params) < 0) {
+		debug("first data training fail!\n");
+		reg = readl(&publ->datx8[0].dxgsr[0]);
+		/* Check the result for rank 0. */
+		if (channel == 0 && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
+			debug("data training fail!\n");
+			return -EIO;
+		}
+
+		/* Check the result for rank 1. */
+		if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
+			sdram_params->ch[channel].rank = 1;
+			clrsetbits_le32(&publ->pgcr, 0xF << 18,
+					sdram_params->ch[channel].rank << 18);
+			need_trainig = 1;
+		}
+		reg = readl(&publ->datx8[2].dxgsr[0]);
+		if (reg & (1 << 4)) {
+			sdram_params->ch[channel].bw = 1;
+			rk3066_dmc_set_bandwidth_ratio(chan, channel,
+						       sdram_params->ch[channel].bw,
+						       dram->grf);
+			need_trainig = 1;
+		}
+	}
+	/* Assume that the die bit width is equel to the chip bit width. */
+	sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
+
+	if (need_trainig &&
+	    (rk3066_dmc_data_training(chan, channel, sdram_params) < 0)) {
+		if (sdram_params->base.dramtype == LPDDR3) {
+			rk3066_dmc_ddr_phy_ctl_reset(dram->cru, channel, 1);
+			udelay(10);
+			rk3066_dmc_ddr_phy_ctl_reset(dram->cru, channel, 0);
+			udelay(10);
+		}
+		debug("2nd data training failed!");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int rk3066_dmc_sdram_col_row_detect(struct rk3066_dmc_dram_info *dram, int channel,
+					   struct rk3066_dmc_sdram_params *sdram_params)
+{
+	int row, col;
+	unsigned int addr;
+	const struct rk3066_dmc_chan_info *chan = &dram->chan[channel];
+	struct rk3288_ddr_pctl *pctl = chan->pctl;
+	struct rk3288_ddr_publ *publ = chan->publ;
+	int ret = 0;
+
+	/* Detect col. */
+	for (col = 11; col >= 9; col--) {
+		writel(0, CONFIG_SYS_SDRAM_BASE);
+		addr = CONFIG_SYS_SDRAM_BASE +
+		       (1 << (col + sdram_params->ch[channel].bw - 1));
+		writel(TEST_PATTERN, addr);
+		if ((readl(addr) == TEST_PATTERN) &&
+		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+			break;
+	}
+	if (col == 8) {
+		debug("Col detect error\n");
+		ret = -EINVAL;
+		goto out;
+	} else {
+		sdram_params->ch[channel].col = col;
+	}
+
+	rk3066_dmc_ddr_rank_2_row15en(dram->grf, 1);
+	rk3066_dmc_move_to_config_state(publ, pctl);
+	writel(1, &chan->msch->ddrconf);
+	rk3066_dmc_move_to_access_state(chan);
+	/* Detect row, max 15, min13 for rk3066 */
+	for (row = 16; row >= 13; row--) {
+		writel(0, CONFIG_SYS_SDRAM_BASE);
+		addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+		writel(TEST_PATTERN, addr);
+		if ((readl(addr) == TEST_PATTERN) &&
+		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+			break;
+	}
+	if (row == 12) {
+		debug("Row detect error\n");
+		ret = -EINVAL;
+	} else {
+		sdram_params->ch[channel].cs1_row = row;
+		sdram_params->ch[channel].row_3_4 = 0;
+		debug("chn %d col %d, row %d\n", channel, col, row);
+		sdram_params->ch[channel].cs0_row = row;
+	}
+
+out:
+	return ret;
+}
+
+static int rk3066_dmc_sdram_get_niu_config(struct rk3066_dmc_sdram_params *sdram_params)
+{
+	int i, tmp, size, ret = 0;
+
+	tmp = sdram_params->ch[0].col - 9;
+	tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
+	tmp |= ((sdram_params->ch[0].cs0_row - 13) << 4);
+	size = ARRAY_SIZE(rk3066_dmc_ddrconf_table) / sizeof(rk3066_dmc_ddrconf_table[0]);
+	for (i = 0; i < size; i++)
+		if (tmp == rk3066_dmc_ddrconf_table[i])
+			break;
+	if (i >= size) {
+		debug("niu config not found\n");
+		ret = -EINVAL;
+	} else {
+		debug("niu config %d\n", i);
+		sdram_params->base.ddrconfig = i;
+	}
+
+	return ret;
+}
+
+static int rk3066_dmc_sdram_init(struct rk3066_dmc_dram_info *dram,
+				 struct rk3066_dmc_sdram_params *sdram_params)
+{
+	int channel;
+	int zqcr;
+	int ret;
+
+	if ((sdram_params->base.dramtype == DDR3 &&
+	     sdram_params->base.ddr_freq > 800000000)) {
+		debug("SDRAM frequency is too high!");
+		return -E2BIG;
+	}
+
+	ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
+	if (ret) {
+		debug("Could not set DDR clock\n");
+		return ret;
+	}
+
+	for (channel = 0; channel < 1; channel++) {
+		const struct rk3066_dmc_chan_info *chan = &dram->chan[channel];
+		struct rk3288_ddr_pctl *pctl = chan->pctl;
+		struct rk3288_ddr_publ *publ = chan->publ;
+
+		rk3066_dmc_phy_pctrl_reset(dram->cru, publ, channel);
+		rk3066_dmc_phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
+
+		rk3066_dmc_dfi_cfg(pctl, sdram_params->base.dramtype);
+
+		rk3066_dmc_pctl_cfg(channel, pctl, sdram_params, dram->grf);
+
+		rk3066_dmc_phy_cfg(chan, channel, sdram_params);
+
+		rk3066_dmc_phy_init(publ);
+
+		writel(POWER_UP_START, &pctl->powctl);
+		while (!(readl(&pctl->powstat) & POWER_UP_DONE))
+			;
+
+		rk3066_dmc_memory_init(publ, sdram_params->base.dramtype);
+		rk3066_dmc_move_to_config_state(publ, pctl);
+
+		/* Use 32bit bus width for detection. */
+		sdram_params->ch[channel].bw = 2;
+		rk3066_dmc_set_bandwidth_ratio(chan, channel,
+					       sdram_params->ch[channel].bw, dram->grf);
+		/*
+		 * set cs, using n=3 for detect
+		 * CS0, n=1
+		 * CS1, n=2
+		 * CS0 & CS1, n = 3
+		 */
+		sdram_params->ch[channel].rank = 2;
+		clrsetbits_le32(&publ->pgcr, 0xF << 18,
+				(sdram_params->ch[channel].rank | 1) << 18);
+
+		/* DS=40ohm,ODT=155ohm */
+		zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
+		       2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
+		       0x19 << PD_OUTPUT_SHIFT;
+		writel(zqcr, &publ->zq1cr[0]);
+		writel(zqcr, &publ->zq0cr[0]);
+
+		/* Detect the rank and bit-width with data-training. */
+		writel(1, &chan->msch->ddrconf);
+		rk3066_dmc_sdram_rank_bw_detect(dram, channel, sdram_params);
+
+		if (sdram_params->base.dramtype == LPDDR3) {
+			u32 i;
+
+			writel(0, &pctl->mrrcfg0);
+
+			for (i = 0; i < 17; i++)
+				rk3066_dmc_send_command_op(pctl, 1, MRR_CMD, i, 0);
+		}
+		writel(4, &chan->msch->ddrconf);
+		rk3066_dmc_move_to_access_state(chan);
+		/* DDR3 and LPDDR3 are always 8 bank, no need to detect. */
+		sdram_params->ch[channel].bk = 3;
+		/* Detect Col and Row number. */
+		ret = rk3066_dmc_sdram_col_row_detect(dram, channel, sdram_params);
+		if (ret)
+			goto error;
+	}
+	/* Find NIU DDR configuration. */
+	ret = rk3066_dmc_sdram_get_niu_config(sdram_params);
+	if (ret)
+		goto error;
+
+	rk3066_dmc_dram_all_config(dram, sdram_params);
+	debug("SDRAM init OK!\n");
+
+	return 0;
+error:
+	debug("SDRAM init failed!\n");
+	hang();
+}
+
+static int rk3066_dmc_setup_sdram(struct udevice *dev)
+{
+	struct rk3066_dmc_dram_info *priv = dev_get_priv(dev);
+	struct rk3066_dmc_sdram_params *params = dev_get_plat(dev);
+
+	return rk3066_dmc_sdram_init(priv, params);
+}
+
+static int rk3066_dmc_conv_of_plat(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct rk3066_dmc_sdram_params *plat = dev_get_plat(dev);
+	struct dtd_rockchip_rk3066_dmc *of_plat = &plat->of_plat;
+	int ret;
+
+	memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
+	       sizeof(plat->pctl_timing));
+	memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
+	       sizeof(plat->phy_timing));
+	memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
+	/* RK3066 supports dual-channel, set default channel num to 2. */
+	plat->num_channels = 1;
+	ret = regmap_init_mem_plat(dev, of_plat->reg,
+				   ARRAY_SIZE(of_plat->reg) / 2, &plat->map);
+	if (ret)
+		return ret;
+
+	return 0;
+#else
+	return -EINVAL;
+#endif
+}
+
+static int rk3066_dmc_probe(struct udevice *dev)
+{
+	struct rk3066_dmc_dram_info *priv = dev_get_priv(dev);
+
+	priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
+
+	if (IS_ENABLED(CONFIG_TPL_BUILD)) {
+		struct rk3066_dmc_sdram_params *plat = dev_get_plat(dev);
+		struct regmap *map;
+		struct udevice *dev_clk;
+		int ret;
+
+		ret = rk3066_dmc_conv_of_plat(dev);
+		if (ret)
+			return ret;
+
+		map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
+		if (IS_ERR(map))
+			return PTR_ERR(map);
+		priv->chan[0].msch = regmap_get_range(map, 0);
+		priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+		priv->chan[0].pctl = regmap_get_range(plat->map, 0);
+		priv->chan[0].publ = regmap_get_range(plat->map, 1);
+
+		ret = rockchip_get_clk(&dev_clk);
+		if (ret)
+			return ret;
+
+		priv->ddr_clk.id = CLK_DDR;
+		ret = clk_request(dev_clk, &priv->ddr_clk);
+		if (ret)
+			return ret;
+
+		priv->cru = rockchip_get_cru();
+		if (IS_ERR(priv->cru))
+			return PTR_ERR(priv->cru);
+
+		ret = rk3066_dmc_setup_sdram(dev);
+		if (ret)
+			return ret;
+	} else {
+		priv->info.base = CONFIG_SYS_SDRAM_BASE;
+		priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmu->sys_reg[2]);
+	}
+
+	return 0;
+}
+
+static int rk3066_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+	struct rk3066_dmc_dram_info *priv = dev_get_priv(dev);
+
+	*info = priv->info;
+
+	return 0;
+}
+
+static struct ram_ops rk3066_dmc_ops = {
+	.get_info = rk3066_dmc_get_info,
+};
+
+static const struct udevice_id rk3066_dmc_ids[] = {
+	{ .compatible = "rockchip,rk3066-dmc" },
+	{ }
+};
+
+U_BOOT_DRIVER(rockchip_rk3066_dmc) = {
+	.name		= "rockchip_rk3066_dmc",
+	.id		= UCLASS_RAM,
+	.ops		= &rk3066_dmc_ops,
+	.probe		= rk3066_dmc_probe,
+	.of_match	= rk3066_dmc_ids,
+	.priv_auto	= sizeof(struct rk3066_dmc_dram_info),
+#if IS_ENABLED(CONFIG_TPL_BUILD)
+	.plat_auto	= sizeof(struct rk3066_dmc_sdram_params),
+#endif
+};
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index dc514c95d3..1e595d0600 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -762,10 +762,11 @@ config PL01X_SERIAL
 
 config ROCKCHIP_SERIAL
 	bool "Rockchip on-chip UART support"
-	depends on DM_SERIAL && SPL_OF_PLATDATA
+	depends on DM_SERIAL
+	select SYS_NS16550
 	help
 	  Select this to enable a debug UART for Rockchip devices when using
-	  CONFIG_SPL_OF_PLATDATA (i.e. a compiled-in device tree replacemenmt).
+	  OF_PLATDATA (i.e. a compiled-in device tree replacemenmt).
 	  This uses the ns16550 driver, converting the platdata from of-platdata
 	  to the ns16550 format.
 
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index b68b5e7b2b..d8e26d72ea 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -46,9 +46,7 @@ obj-$(CONFIG_MXC_UART) += serial_mxc.o
 obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
 obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
 obj-$(CONFIG_INTEL_MID_SERIAL) += serial_intel_mid.o
-ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
-endif
 obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
 obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
 obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 796ff1658c..a4220fd0ae 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -624,8 +624,6 @@ U_BOOT_DRIVER(ns16550_serial) = {
 #endif
 };
 
-DM_DRIVER_ALIAS(ns16550_serial, rockchip_rk3328_uart)
-DM_DRIVER_ALIAS(ns16550_serial, rockchip_rk3368_uart)
 DM_DRIVER_ALIAS(ns16550_serial, ti_da830_uart)
 #endif
 #endif /* SERIAL_PRESENT */
diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c
index 97d40869a2..f4e9422ed9 100644
--- a/drivers/serial/serial_rockchip.c
+++ b/drivers/serial/serial_rockchip.c
@@ -12,22 +12,20 @@
 #include <asm/arch-rockchip/clock.h>
 #include <dm/device-internal.h>
 
-#if defined(CONFIG_ROCKCHIP_RK3188)
 struct rockchip_uart_plat {
-	struct dtd_rockchip_rk3188_uart dtplat;
-	struct ns16550_plat plat;
-};
-struct dtd_rockchip_rk3188_uart *dtplat, s_dtplat;
-#elif defined(CONFIG_ROCKCHIP_RK3288)
-struct rockchip_uart_plat {
-	struct dtd_rockchip_rk3288_uart dtplat;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_rockchip_uart dtplat;
+#endif
 	struct ns16550_plat plat;
 };
-struct dtd_rockchip_rk3288_uart *dtplat, s_dtplat;
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+struct dtd_rockchip_uart *dtplat, s_dtplat;
 #endif
 
 static int rockchip_serial_probe(struct udevice *dev)
 {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct rockchip_uart_plat *plat = dev_get_plat(dev);
 
 	/* Create some new platform data for the standard driver */
@@ -38,24 +36,22 @@ static int rockchip_serial_probe(struct udevice *dev)
 	dev_set_plat(dev, &plat->plat);
 
 	return ns16550_serial_probe(dev);
+#else
+	return -ENODEV;
+#endif
 }
 
-U_BOOT_DRIVER(rockchip_rk3188_uart) = {
-	.name	= "rockchip_rk3188_uart",
-	.id	= UCLASS_SERIAL,
-	.priv_auto	= sizeof(struct ns16550),
-	.plat_auto	= sizeof(struct rockchip_uart_plat),
-	.probe	= rockchip_serial_probe,
-	.ops	= &ns16550_serial_ops,
-	.flags	= DM_FLAG_PRE_RELOC,
-};
-
-U_BOOT_DRIVER(rockchip_rk3288_uart) = {
-	.name	= "rockchip_rk3288_uart",
-	.id	= UCLASS_SERIAL,
+U_BOOT_DRIVER(rockchip_uart) = {
+	.name		= "rockchip_uart",
+	.id		= UCLASS_SERIAL,
 	.priv_auto	= sizeof(struct ns16550),
 	.plat_auto	= sizeof(struct rockchip_uart_plat),
-	.probe	= rockchip_serial_probe,
-	.ops	= &ns16550_serial_ops,
-	.flags	= DM_FLAG_PRE_RELOC,
+	.probe		= rockchip_serial_probe,
+	.ops		= &ns16550_serial_ops,
+	.flags		= DM_FLAG_PRE_RELOC,
 };
+DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3066_uart)
+DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3188_uart)
+DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3288_uart)
+DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3328_uart)
+DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3368_uart)
diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
index e098addddc..851a648298 100644
--- a/drivers/spi/rockchip_sfc.c
+++ b/drivers/spi/rockchip_sfc.c
@@ -12,6 +12,7 @@
 #include <bouncebuf.h>
 #include <clk.h>
 #include <dm.h>
+#include <dm/device_compat.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
 #include <linux/iopoll.h>
diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c
index 9aed5dd217..10f0a9f646 100644
--- a/drivers/timer/dw-apb-timer.c
+++ b/drivers/timer/dw-apb-timer.c
@@ -8,10 +8,12 @@
 #include <common.h>
 #include <dm.h>
 #include <clk.h>
+#include <dt-structs.h>
 #include <malloc.h>
 #include <reset.h>
 #include <timer.h>
 #include <dm/device_compat.h>
+#include <linux/kconfig.h>
 
 #include <asm/io.h>
 #include <asm/arch/timer.h>
@@ -25,6 +27,12 @@ struct dw_apb_timer_priv {
 	struct reset_ctl_bulk resets;
 };
 
+struct dw_apb_timer_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_snps_dw_apb_timer dtplat;
+#endif
+};
+
 static u64 dw_apb_timer_get_count(struct udevice *dev)
 {
 	struct dw_apb_timer_priv *priv = dev_get_priv(dev);
@@ -43,20 +51,33 @@ static int dw_apb_timer_probe(struct udevice *dev)
 	struct dw_apb_timer_priv *priv = dev_get_priv(dev);
 	struct clk clk;
 	int ret;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dw_apb_timer_plat *plat = dev_get_plat(dev);
+	struct dtd_snps_dw_apb_timer *dtplat = &plat->dtplat;
 
-	ret = reset_get_bulk(dev, &priv->resets);
-	if (ret)
-		dev_warn(dev, "Can't get reset: %d\n", ret);
-	else
-		reset_deassert_bulk(&priv->resets);
+	priv->regs = dtplat->reg[0];
 
-	ret = clk_get_by_index(dev, 0, &clk);
-	if (ret)
+	ret = clk_get_by_phandle(dev, &dtplat->clocks[0], &clk);
+	if (ret < 0)
 		return ret;
 
-	uc_priv->clock_rate = clk_get_rate(&clk);
+	uc_priv->clock_rate = dtplat->clock_frequency;
+#endif
+	if (CONFIG_IS_ENABLED(OF_REAL)) {
+		ret = reset_get_bulk(dev, &priv->resets);
+		if (ret)
+			dev_warn(dev, "Can't get reset: %d\n", ret);
+		else
+			reset_deassert_bulk(&priv->resets);
+
+		ret = clk_get_by_index(dev, 0, &clk);
+		if (ret)
+			return ret;
 
-	clk_free(&clk);
+		uc_priv->clock_rate = clk_get_rate(&clk);
+
+		clk_free(&clk);
+	}
 
 	/* init timer */
 	writel(0xffffffff, priv->regs + DW_APB_LOAD_VAL);
@@ -68,9 +89,11 @@ static int dw_apb_timer_probe(struct udevice *dev)
 
 static int dw_apb_timer_of_to_plat(struct udevice *dev)
 {
-	struct dw_apb_timer_priv *priv = dev_get_priv(dev);
+	if (CONFIG_IS_ENABLED(OF_REAL)) {
+		struct dw_apb_timer_priv *priv = dev_get_priv(dev);
 
-	priv->regs = dev_read_addr(dev);
+		priv->regs = dev_read_addr(dev);
+	}
 
 	return 0;
 }
@@ -91,13 +114,14 @@ static const struct udevice_id dw_apb_timer_ids[] = {
 	{}
 };
 
-U_BOOT_DRIVER(dw_apb_timer) = {
-	.name		= "dw_apb_timer",
+U_BOOT_DRIVER(snps_dw_apb_timer) = {
+	.name		= "snps_dw_apb_timer",
 	.id		= UCLASS_TIMER,
 	.ops		= &dw_apb_timer_ops,
 	.probe		= dw_apb_timer_probe,
 	.of_match	= dw_apb_timer_ids,
-	.of_to_plat = dw_apb_timer_of_to_plat,
+	.of_to_plat	= dw_apb_timer_of_to_plat,
 	.remove		= dw_apb_timer_remove,
 	.priv_auto	= sizeof(struct dw_apb_timer_priv),
+	.plat_auto	= sizeof(struct dw_apb_timer_plat),
 };
diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c
index 7e48dd8346..c0dffa3cba 100644
--- a/drivers/video/rockchip/rk3288_mipi.c
+++ b/drivers/video/rockchip/rk3288_mipi.c
@@ -174,6 +174,7 @@ static const struct dm_display_ops rk_mipi_dsi_ops = {
 };
 
 static const struct udevice_id rk_mipi_dsi_ids[] = {
+	{ .compatible = "rockchip,rk3288-mipi-dsi" },
 	{ .compatible = "rockchip,rk3288_mipi_dsi" },
 	{ }
 };
diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c
index 9173350483..7fc79ba904 100644
--- a/drivers/video/rockchip/rk3399_mipi.c
+++ b/drivers/video/rockchip/rk3399_mipi.c
@@ -165,6 +165,7 @@ static const struct dm_display_ops rk_mipi_dsi_ops = {
 };
 
 static const struct udevice_id rk_mipi_dsi_ids[] = {
+	{ .compatible = "rockchip,rk3399-mipi-dsi" },
 	{ .compatible = "rockchip,rk3399_mipi_dsi" },
 	{ }
 };
diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c
index 0ddf5e02d6..3697d58251 100644
--- a/drivers/video/rockchip/rk_edp.c
+++ b/drivers/video/rockchip/rk_edp.c
@@ -1070,8 +1070,11 @@ static int rk_edp_probe(struct udevice *dev)
 
 	ret = reset_get_by_name(dev, "dp", &dp_rst);
 	if (ret) {
-		dev_err(dev, "failed to get dp reset (ret=%d)\n", ret);
-		return ret;
+		ret = reset_get_by_name(dev, "edp", &dp_rst);
+		if (ret) {
+			dev_err(dev, "failed to get dp reset (ret=%d)\n", ret);
+			return ret;
+		}
 	}
 
 	ret = reset_assert(&dp_rst);
@@ -1156,6 +1159,7 @@ static const struct rockchip_dp_data rk3288_dp = {
 };
 
 static const struct udevice_id rockchip_dp_ids[] = {
+	{ .compatible = "rockchip,rk3288-dp", .data = (ulong)&rk3288_dp },
 	{ .compatible = "rockchip,rk3288-edp", .data = (ulong)&rk3288_dp },
 	{ .compatible = "rockchip,rk3399-edp", .data = (ulong)&rk3399_edp },
 	{ }