diff options
author | Tom Rini <trini@konsulko.com> | 2023-01-26 21:07:06 +0300 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2023-01-26 21:07:06 +0300 |
commit | b6904cc98a9168180bbed5f95d046724a188513c (patch) | |
tree | 5ada11ad4b092365a2062fc69730558e2cb2f054 /drivers | |
parent | 27e0fb3b0823519aea2d42cd8bde20234dd87cef (diff) | |
parent | 87a6d86571268be4e354fe030c53745a54f4ed8e (diff) | |
download | u-boot-b6904cc98a9168180bbed5f95d046724a188513c.tar.xz |
Merge https://source.denx.de/u-boot/custodians/u-boot-spi
- fix return code of sf command (Heinrich)
- fix register reads in STIG Mode (Dhruva)
- Infineon s25fs256t support (Takahiro)
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/mtd/spi/spi-nor-core.c | 95 | ||||
-rw-r--r-- | drivers/mtd/spi/spi-nor-ids.c | 2 | ||||
-rw-r--r-- | drivers/spi/Kconfig | 8 | ||||
-rw-r--r-- | drivers/spi/Makefile | 1 | ||||
-rw-r--r-- | drivers/spi/bcm63xx_hsspi.c | 2 | ||||
-rw-r--r-- | drivers/spi/cadence_qspi.c | 10 | ||||
-rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 13 | ||||
-rw-r--r-- | drivers/spi/fsl_dspi.c | 4 | ||||
-rw-r--r-- | drivers/spi/mtk_snfi_spi.c | 4 | ||||
-rw-r--r-- | drivers/spi/mvebu_a3700_spi.c | 2 | ||||
-rw-r--r-- | drivers/spi/omap3_spi.c | 2 | ||||
-rw-r--r-- | drivers/spi/rk_spi.c | 2 | ||||
-rw-r--r-- | drivers/spi/sh_qspi.c | 4 | ||||
-rw-r--r-- | drivers/spi/spi-aspeed-smc.c | 4 | ||||
-rw-r--r-- | drivers/spi/spi-qup.c | 2 | ||||
-rw-r--r-- | drivers/spi/spi-sifive.c | 2 | ||||
-rw-r--r-- | drivers/spi/spi-sn-f-ospi.c | 686 |
17 files changed, 795 insertions, 48 deletions
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 1ea8363d9f..2c3116ee53 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3195,7 +3195,11 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, } #ifdef CONFIG_SPI_FLASH_SPANSION -static int s25hx_t_mdp_ready(struct spi_nor *nor) + +/* Use ID byte 4 to distinguish S25FS256T and S25Hx-T */ +#define S25FS256T_ID4 (0x08) + +static int s25_mdp_ready(struct spi_nor *nor) { u32 addr; int ret; @@ -3209,7 +3213,7 @@ static int s25hx_t_mdp_ready(struct spi_nor *nor) return 1; } -static int s25hx_t_quad_enable(struct spi_nor *nor) +static int s25_quad_enable(struct spi_nor *nor) { u32 addr; int ret; @@ -3223,51 +3227,67 @@ static int s25hx_t_quad_enable(struct spi_nor *nor) return 0; } -static int s25hx_t_erase_non_uniform(struct spi_nor *nor, loff_t addr) +static int s25_erase_non_uniform(struct spi_nor *nor, loff_t addr) { /* Support 32 x 4KB sectors at bottom */ return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, SZ_128K); } -static int s25hx_t_setup(struct spi_nor *nor, const struct flash_info *info, - const struct spi_nor_flash_parameter *params) +static int s25_setup(struct spi_nor *nor, const struct flash_info *info, + const struct spi_nor_flash_parameter *params) { int ret; - u8 cfr3v; + u8 cr; #ifdef CONFIG_SPI_FLASH_BAR return -ENOTSUPP; /* Bank Address Register is not supported */ #endif /* + * S25FS256T has multiple sector architecture options, with selection of + * count and location of 128KB and 64KB sectors. This driver supports + * uniform 128KB only due to complexity of non-uniform layout. + */ + if (nor->info->id[4] == S25FS256T_ID4) { + ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_ARCFN, 8, &cr); + if (ret) + return ret; + + if (cr) /* Option 0 (ARCFN[7:0] == 0x00) is uniform */ + return -EOPNOTSUPP; + + return spi_nor_default_setup(nor, info, params); + } + + /* * Read CFR3V to check if uniform sector is selected. If not, assign an * erase hook that supports non-uniform erase. */ - ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, 0, &cfr3v); + ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, 0, &cr); if (ret) return ret; - if (!(cfr3v & CFR3V_UNHYSA)) - nor->erase = s25hx_t_erase_non_uniform; + if (!(cr & CFR3V_UNHYSA)) + nor->erase = s25_erase_non_uniform; /* * For the multi-die package parts, the ready() hook is needed to check * all dies' status via read any register. */ if (nor->mtd.size > SZ_128M) - nor->ready = s25hx_t_mdp_ready; + nor->ready = s25_mdp_ready; return spi_nor_default_setup(nor, info, params); } -static void s25hx_t_default_init(struct spi_nor *nor) +static void s25_default_init(struct spi_nor *nor) { - nor->setup = s25hx_t_setup; + nor->setup = s25_setup; } -static int s25hx_t_post_bfpt_fixup(struct spi_nor *nor, - const struct sfdp_parameter_header *header, - const struct sfdp_bfpt *bfpt, - struct spi_nor_flash_parameter *params) +static int s25_post_bfpt_fixup(struct spi_nor *nor, + const struct sfdp_parameter_header *header, + const struct sfdp_bfpt *bfpt, + struct spi_nor_flash_parameter *params) { int ret; u32 addr; @@ -3296,6 +3316,10 @@ static int s25hx_t_post_bfpt_fixup(struct spi_nor *nor, nor->addr_mode_nbytes = 4; } + /* The default address mode in S25FS256T is 4. */ + if (nor->info->id[4] == S25FS256T_ID4) + nor->addr_mode_nbytes = 4; + /* * The page_size is set to 512B from BFPT, but it actually depends on * the configuration register. Look up the CFR3V and determine the @@ -3318,21 +3342,26 @@ static int s25hx_t_post_bfpt_fixup(struct spi_nor *nor, return 0; } -static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor, - struct spi_nor_flash_parameter *params) +static void s25_post_sfdp_fixup(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) { - /* READ_FAST_4B (0Ch) requires mode cycles*/ - params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; - /* PP_1_1_4 is not supported */ - params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; - /* Use volatile register to enable quad */ - params->quad_enable = s25hx_t_quad_enable; + if (nor->info->id[4] == S25FS256T_ID4) { + /* PP_1_1_4 is supported */ + params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; + } else { + /* READ_FAST_4B (0Ch) requires mode cycles*/ + params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; + /* PP_1_1_4 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; + /* Use volatile register to enable quad */ + params->quad_enable = s25_quad_enable; + } } -static struct spi_nor_fixups s25hx_t_fixups = { - .default_init = s25hx_t_default_init, - .post_bfpt = s25hx_t_post_bfpt_fixup, - .post_sfdp = s25hx_t_post_sfdp_fixup, +static struct spi_nor_fixups s25_fixups = { + .default_init = s25_default_init, + .post_bfpt = s25_post_bfpt_fixup, + .post_sfdp = s25_post_sfdp_fixup, }; static int s25fl256l_setup(struct spi_nor *nor, const struct flash_info *info, @@ -3373,7 +3402,7 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor) if (ret) return ret; - buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24; + buf = SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24; op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR2V, 1), SPI_MEM_OP_NO_DUMMY, @@ -3396,7 +3425,7 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor) if (ret) return ret; - buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; + buf = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN; op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR5V, 1), SPI_MEM_OP_NO_DUMMY, @@ -3444,7 +3473,7 @@ static int s28hx_t_setup(struct spi_nor *nor, const struct flash_info *info, if (ret) return ret; - if (!(buf & SPINOR_REG_CYPRESS_CFR3V_UNISECT)) + if (!(buf & SPINOR_REG_CYPRESS_CFR3_UNISECT)) nor->erase = s28hx_t_erase_non_uniform; return spi_nor_default_setup(nor, info, params); @@ -3511,7 +3540,7 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor, if (ret) return ret; - if (buf & SPINOR_REG_CYPRESS_CFR3V_PGSZ) + if (buf & SPINOR_REG_CYPRESS_CFR3_PGSZ) params->page_size = 512; else params->page_size = 256; @@ -3850,7 +3879,7 @@ void spi_nor_set_fixups(struct spi_nor *nor) switch (nor->info->id[1]) { case 0x2a: /* S25HL (QSPI, 3.3V) */ case 0x2b: /* S25HS (QSPI, 1.8V) */ - nor->fixups = &s25hx_t_fixups; + nor->fixups = &s25_fixups; break; #ifdef CONFIG_SPI_FLASH_S28HX_T diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 5f8f3ec955..a862fbd707 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -294,6 +294,8 @@ const struct flash_info spi_nor_ids[] = { USE_CLSR) }, { INFO6("s25hs02gt", 0x342b1c, 0x0f0090, 256 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO6("s25fs256t", 0x342b19, 0x0f0890, 128 * 1024, 256, + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, #ifdef CONFIG_SPI_FLASH_S28HX_T { INFO("s28hl512t", 0x345a1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) }, { INFO("s28hl01gt", 0x345a1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) }, diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 64ceed12ce..cdd2304aeb 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -461,6 +461,14 @@ config SOFT_SPI Enable Soft SPI driver. This driver is to use GPIO simulate the SPI protocol. +config SPI_SN_F_OSPI + tristate "Socionext F_OSPI SPI flash controller" + depends on SPI_MEM + help + This enables support for the Socionext F_OSPI controller + for connecting an SPI flash memory over up to 8-bit wide bus. + It supports indirect access mode only. + config SPI_SUNXI bool "Allwinner SoC SPI controllers" default ARCH_SUNXI diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 674d81caae..95dba9ac45 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_ROCKCHIP_SFC) += rockchip_sfc.o obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o +obj-$(CONFIG_SPI_SN_F_OSPI) += spi-sn-f-ospi.o obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.o obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index 47002f8b56..4d714adc4a 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -210,7 +210,7 @@ static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv) * claimed. This way, the dummy CS is restored to its inactive value when * transfers are issued and the desired CS is preserved in its active value * all the time. This hack is also used in the upstream linux driver and - * allows keeping CS active between trasnfers even if the HW doesn't give + * allows keeping CS active between transfers even if the HW doesn't give * this possibility. */ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index ab0a681c83..328dfb0a38 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -307,7 +307,13 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, priv->is_decoded_cs); if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { - if (!op->addr.nbytes) + /* + * Performing reads in DAC mode forces to read minimum 4 bytes + * which is unsupported on some flash devices during register + * reads, prefer STIG mode for such small reads. + */ + if (!op->addr.nbytes || + op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) mode = CQSPI_STIG_READ; else mode = CQSPI_READ; @@ -392,7 +398,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus) plat->is_dma = dev_read_bool(bus, "cdns,is-dma"); - /* All other paramters are embedded in the child node */ + /* All other parameters are embedded in the child node */ subnode = dev_read_first_subnode(bus); if (!ofnode_valid(subnode)) { printf("Error: subnode with SPI flash config missing!\n"); diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index d1f89138ef..21fe2e655c 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -479,6 +479,19 @@ int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv, /* 0 means 1 byte. */ reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); + + /* setup ADDR BIT field */ + if (op->addr.nbytes) { + writel(op->addr.val, priv->regbase + CQSPI_REG_CMDADDRESS); + /* + * address bytes are zero indexed + */ + reg |= (((op->addr.nbytes - 1) & + CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) << + CQSPI_REG_CMDCTRL_ADD_BYTES_LSB); + reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); + } + status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg); if (status != 0) return status; diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index 62444e408a..8e5cc5552f 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -491,7 +491,7 @@ static int fsl_dspi_probe(struct udevice *bus) dm_spi_bus = dev_get_uclass_priv(bus); - /* cpu speical pin muxing configure */ + /* cpu special pin muxing configure */ cpu_dspi_port_conf(); /* get input clk frequency */ @@ -600,7 +600,7 @@ static int fsl_dspi_of_to_plat(struct udevice *bus) plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ); - debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n", + debug("DSPI: regs=%pa, max-frequency=%d, endianness=%s, num-cs=%d\n", &plat->regs_addr, plat->speed_hz, plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le", plat->num_chipselect); diff --git a/drivers/spi/mtk_snfi_spi.c b/drivers/spi/mtk_snfi_spi.c index 5ea62776b4..3decb3744d 100644 --- a/drivers/spi/mtk_snfi_spi.c +++ b/drivers/spi/mtk_snfi_spi.c @@ -153,7 +153,7 @@ static void mtk_snfi_copy_to_gpram(struct mtk_snfi_priv *priv, /* * The output data will always be copied to the beginning of - * the GPRAM. Uses word write for better performace. + * the GPRAM. Uses word write for better performance. * * Trailing bytes in the last word are not cared. */ @@ -180,7 +180,7 @@ static void mtk_snfi_copy_from_gpram(struct mtk_snfi_priv *priv, u8 *cache, /* * Read aligned data from GPRAM to buffer first. - * Uses word read for better performace. + * Uses word read for better performance. */ i = 0; while (pos < end) { diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c index b1dce048ad..52882e8b26 100644 --- a/drivers/spi/mvebu_a3700_spi.c +++ b/drivers/spi/mvebu_a3700_spi.c @@ -84,7 +84,7 @@ static void spi_cs_deactivate(struct mvebu_spi_plat *plat, int cs) * The XFER_RDY flag is checked every time before accessing SPI_DOUT * and SPI_DIN register. * - * The number of transfers to be triggerred is decided by @bytelen. + * The number of transfers to be triggered is decided by @bytelen. * * Return: 0 - cool * -ETIMEDOUT - XFER_RDY flag timeout diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index ea38a0ffba..1cbb5d46fd 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -142,7 +142,7 @@ static int omap3_spi_read(struct omap3_spi_priv *priv, unsigned int len, } } - /* Disable the channel to prevent furher receiving */ + /* Disable the channel to prevent further receiving */ if (i == (len - 1)) omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS); diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index cb80be77ae..66b20fce9b 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -485,7 +485,7 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, /* * In case that there's a transmit-component, we need to wait * until the control goes idle before we can disable the SPI - * control logic (as this will implictly flush the FIFOs). + * control logic (as this will implicitly flush the FIFOs). */ if (out) { ret = rkspi_wait_till_not_busy(regs); diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c index 5ba8a8ea79..861423bef3 100644 --- a/drivers/spi/sh_qspi.c +++ b/drivers/spi/sh_qspi.c @@ -6,6 +6,8 @@ * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> */ +#define LOG_CATEGORY UCLASS_SPI + #include <common.h> #include <console.h> #include <malloc.h> @@ -160,7 +162,7 @@ static int sh_qspi_xfer_common(struct sh_qspi_slave *ss, unsigned int bitlen, } if (bitlen % 8) { - printf("%s: bitlen is not 8bit alined %d", __func__, bitlen); + log_warning("bitlen is not 8bit aligned %d", bitlen); return 1; } diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index a3c9633382..4b6ea9f8e9 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -270,7 +270,7 @@ static int ast2500_adjust_decoded_size(struct udevice *bus) flashes[cs].ahb_decoded_sz = priv->info->min_decoded_sz; /* - * If commnad mode or normal mode is used, the start address of a + * If command mode or normal mode is used, the start address of a * decoded range should be multiple of its related flash size. * Namely, the total decoded size from flash 0 to flash N should * be multiple of the size of flash (N + 1). @@ -404,7 +404,7 @@ static int ast2600_adjust_decoded_size(struct udevice *bus) flashes[cs].ahb_decoded_sz = 0; /* - * If commnad mode or normal mode is used, the start address of a + * If command mode or normal mode is used, the start address of a * decoded range should be multiple of its related flash size. * Namely, the total decoded size from flash 0 to flash N should * be multiple of the size of flash (N + 1). diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index cdea5405f6..7b64532e50 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -233,7 +233,7 @@ static unsigned char qup_spi_read_byte(struct udevice *dev) } /* - * Function to check wheather Input or Output FIFO + * Function to check whether Input or Output FIFO * has data to be serviced */ static int qup_spi_check_fifo_status(struct udevice *dev, u32 reg_addr) diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c index 0a00df0ac7..ea372a05f8 100644 --- a/drivers/spi/spi-sifive.c +++ b/drivers/spi/spi-sifive.c @@ -350,7 +350,7 @@ static int sifive_spi_set_speed(struct udevice *bus, uint speed) if (speed > spi->freq) speed = spi->freq; - /* Cofigure max speed */ + /* Configure max speed */ scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1) & SIFIVE_SPI_SCKDIV_DIV_MASK; writel(scale, spi->regs + SIFIVE_SPI_REG_SCKDIV); diff --git a/drivers/spi/spi-sn-f-ospi.c b/drivers/spi/spi-sn-f-ospi.c new file mode 100644 index 0000000000..ebf2903d3e --- /dev/null +++ b/drivers/spi/spi-sn-f-ospi.c @@ -0,0 +1,686 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Socionext SPI flash controller F_OSPI driver + * Copyright (C) 2021 Socionext Inc. + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <spi.h> +#include <spi-mem.h> + +/* Registers */ +#define OSPI_PROT_CTL_INDIR 0x00 +#define OSPI_PROT_MODE_DATA_MASK GENMASK(31, 30) +#define OSPI_PROT_MODE_ALT_MASK GENMASK(29, 28) +#define OSPI_PROT_MODE_ADDR_MASK GENMASK(27, 26) +#define OSPI_PROT_MODE_CODE_MASK GENMASK(25, 24) +#define OSPI_PROT_MODE_SINGLE 0 +#define OSPI_PROT_MODE_DUAL 1 +#define OSPI_PROT_MODE_QUAD 2 +#define OSPI_PROT_MODE_OCTAL 3 +#define OSPI_PROT_DATA_RATE_DATA BIT(23) +#define OSPI_PROT_DATA_RATE_ALT BIT(22) +#define OSPI_PROT_DATA_RATE_ADDR BIT(21) +#define OSPI_PROT_DATA_RATE_CODE BIT(20) +#define OSPI_PROT_SDR 0 +#define OSPI_PROT_DDR 1 +#define OSPI_PROT_BIT_POS_DATA BIT(19) +#define OSPI_PROT_BIT_POS_ALT BIT(18) +#define OSPI_PROT_BIT_POS_ADDR BIT(17) +#define OSPI_PROT_BIT_POS_CODE BIT(16) +#define OSPI_PROT_SAMP_EDGE BIT(12) +#define OSPI_PROT_DATA_UNIT_MASK GENMASK(11, 10) +#define OSPI_PROT_DATA_UNIT_1B 0 +#define OSPI_PROT_DATA_UNIT_2B 1 +#define OSPI_PROT_DATA_UNIT_4B 3 +#define OSPI_PROT_TRANS_DIR_WRITE BIT(9) +#define OSPI_PROT_DATA_EN BIT(8) +#define OSPI_PROT_ALT_SIZE_MASK GENMASK(7, 5) +#define OSPI_PROT_ADDR_SIZE_MASK GENMASK(4, 2) +#define OSPI_PROT_CODE_SIZE_MASK GENMASK(1, 0) + +#define OSPI_CLK_CTL 0x10 +#define OSPI_CLK_CTL_BOOT_INT_CLK_EN BIT(16) +#define OSPI_CLK_CTL_PHA BIT(12) +#define OSPI_CLK_CTL_PHA_180 0 +#define OSPI_CLK_CTL_PHA_90 1 +#define OSPI_CLK_CTL_DIV GENMASK(9, 8) +#define OSPI_CLK_CTL_DIV_1 0 +#define OSPI_CLK_CTL_DIV_2 1 +#define OSPI_CLK_CTL_DIV_4 2 +#define OSPI_CLK_CTL_DIV_8 3 +#define OSPI_CLK_CTL_INT_CLK_EN BIT(0) + +#define OSPI_CS_CTL1 0x14 +#define OSPI_CS_CTL2 0x18 +#define OSPI_SSEL 0x20 +#define OSPI_CMD_IDX_INDIR 0x40 +#define OSPI_ADDR 0x50 +#define OSPI_ALT_INDIR 0x60 +#define OSPI_DMY_INDIR 0x70 +#define OSPI_DAT 0x80 +#define OSPI_DAT_SWP_INDIR 0x90 + +#define OSPI_DAT_SIZE_INDIR 0xA0 +#define OSPI_DAT_SIZE_EN BIT(15) +#define OSPI_DAT_SIZE_MASK GENMASK(10, 0) +#define OSPI_DAT_SIZE_MAX (OSPI_DAT_SIZE_MASK + 1) + +#define OSPI_TRANS_CTL 0xC0 +#define OSPI_TRANS_CTL_STOP_REQ BIT(1) /* RW1AC */ +#define OSPI_TRANS_CTL_START_REQ BIT(0) /* RW1AC */ + +#define OSPI_ACC_MODE 0xC4 +#define OSPI_ACC_MODE_BOOT_DISABLE BIT(0) + +#define OSPI_SWRST 0xD0 +#define OSPI_SWRST_INDIR_WRITE_FIFO BIT(9) /* RW1AC */ +#define OSPI_SWRST_INDIR_READ_FIFO BIT(8) /* RW1AC */ + +#define OSPI_STAT 0xE0 +#define OSPI_STAT_IS_AXI_WRITING BIT(10) +#define OSPI_STAT_IS_AXI_READING BIT(9) +#define OSPI_STAT_IS_SPI_INT_CLK_STOP BIT(4) +#define OSPI_STAT_IS_SPI_IDLE BIT(3) + +#define OSPI_IRQ 0xF0 +#define OSPI_IRQ_CS_DEASSERT BIT(8) +#define OSPI_IRQ_WRITE_BUF_READY BIT(2) +#define OSPI_IRQ_READ_BUF_READY BIT(1) +#define OSPI_IRQ_CS_TRANS_COMP BIT(0) +#define OSPI_IRQ_ALL \ + (OSPI_IRQ_CS_DEASSERT | OSPI_IRQ_WRITE_BUF_READY \ + | OSPI_IRQ_READ_BUF_READY | OSPI_IRQ_CS_TRANS_COMP) + +#define OSPI_IRQ_STAT_EN 0xF4 +#define OSPI_IRQ_SIG_EN 0xF8 + +/* Parameters */ +#define OSPI_NUM_CS 4 +#define OSPI_DUMMY_CYCLE_MAX 255 +#define OSPI_WAIT_MAX_MSEC 100 + +struct f_ospi { + void __iomem *base; + struct udevice *dev; + struct clk clk; + + u32 mode; + u32 max_speed_hz; + u32 num_cs; + u32 chip_select; +}; + +static u32 f_ospi_get_dummy_cycle(const struct spi_mem_op *op) +{ + return (op->dummy.nbytes * 8) / op->dummy.buswidth; +} + +static void f_ospi_clear_irq(struct f_ospi *ospi) +{ + writel(OSPI_IRQ_CS_DEASSERT | OSPI_IRQ_CS_TRANS_COMP, + ospi->base + OSPI_IRQ); +} + +static void f_ospi_enable_irq_status(struct f_ospi *ospi, u32 irq_bits) +{ + u32 val; + + val = readl(ospi->base + OSPI_IRQ_STAT_EN); + val |= irq_bits; + writel(val, ospi->base + OSPI_IRQ_STAT_EN); +} + +static void f_ospi_disable_irq_status(struct f_ospi *ospi, u32 irq_bits) +{ + u32 val; + + val = readl(ospi->base + OSPI_IRQ_STAT_EN); + val &= ~irq_bits; + writel(val, ospi->base + OSPI_IRQ_STAT_EN); +} + +static void f_ospi_disable_irq_output(struct f_ospi *ospi, u32 irq_bits) +{ + u32 val; + + val = readl(ospi->base + OSPI_IRQ_SIG_EN); + val &= ~irq_bits; + writel(val, ospi->base + OSPI_IRQ_SIG_EN); +} + +static int f_ospi_prepare_config(struct f_ospi *ospi) +{ + u32 val, stat0, stat1; + + /* G4: Disable internal clock */ + val = readl(ospi->base + OSPI_CLK_CTL); + val &= ~(OSPI_CLK_CTL_BOOT_INT_CLK_EN | OSPI_CLK_CTL_INT_CLK_EN); + writel(val, ospi->base + OSPI_CLK_CTL); + + /* G5: Wait for stop */ + stat0 = OSPI_STAT_IS_AXI_WRITING | OSPI_STAT_IS_AXI_READING; + stat1 = OSPI_STAT_IS_SPI_IDLE | OSPI_STAT_IS_SPI_INT_CLK_STOP; + + return readl_poll_timeout(ospi->base + OSPI_STAT, + val, (val & (stat0 | stat1)) == stat1, + OSPI_WAIT_MAX_MSEC); +} + +static int f_ospi_unprepare_config(struct f_ospi *ospi) +{ + u32 val; + + /* G11: Enable internal clock */ + val = readl(ospi->base + OSPI_CLK_CTL); + val |= OSPI_CLK_CTL_BOOT_INT_CLK_EN | OSPI_CLK_CTL_INT_CLK_EN; + writel(val, ospi->base + OSPI_CLK_CTL); + + /* G12: Wait for clock to start */ + return readl_poll_timeout(ospi->base + OSPI_STAT, + val, !(val & OSPI_STAT_IS_SPI_INT_CLK_STOP), + OSPI_WAIT_MAX_MSEC); +} + +static void f_ospi_config_clk(struct f_ospi *ospi, u32 device_hz) +{ + long rate_hz = clk_get_rate(&ospi->clk); + u32 div = DIV_ROUND_UP(rate_hz, device_hz); + u32 div_reg; + u32 val; + + if (rate_hz < device_hz) { + dev_warn(ospi->dev, "Device frequency too large: %d\n", + device_hz); + div_reg = OSPI_CLK_CTL_DIV_1; + } else { + if (div == 1) { + div_reg = OSPI_CLK_CTL_DIV_1; + } else if (div == 2) { + div_reg = OSPI_CLK_CTL_DIV_2; + } else if (div <= 4) { + div_reg = OSPI_CLK_CTL_DIV_4; + } else if (div <= 8) { + div_reg = OSPI_CLK_CTL_DIV_8; + } else { + dev_warn(ospi->dev, "Device frequency too small: %d\n", + device_hz); + div_reg = OSPI_CLK_CTL_DIV_8; + } + } + + /* + * G7: Set clock mode + * clock phase is fixed at 180 degrees and configure edge direction + * instead. + */ + val = readl(ospi->base + OSPI_CLK_CTL); + + val &= ~(OSPI_CLK_CTL_PHA | OSPI_CLK_CTL_DIV); + val |= FIELD_PREP(OSPI_CLK_CTL_PHA, OSPI_CLK_CTL_PHA_180) + | FIELD_PREP(OSPI_CLK_CTL_DIV, div_reg); + + writel(val, ospi->base + OSPI_CLK_CTL); +} + +static void f_ospi_config_dll(struct f_ospi *ospi) +{ + /* G8: Configure DLL, nothing */ +} + +static u8 f_ospi_get_mode(struct f_ospi *ospi, int width, int data_size) +{ + u8 mode = OSPI_PROT_MODE_SINGLE; + + switch (width) { + case 1: + mode = OSPI_PROT_MODE_SINGLE; + break; + case 2: + mode = OSPI_PROT_MODE_DUAL; + break; + case 4: + mode = OSPI_PROT_MODE_QUAD; + break; + case 8: + mode = OSPI_PROT_MODE_OCTAL; + break; + default: + if (data_size) + dev_err(ospi->dev, "Invalid buswidth: %d\n", width); + break; + } + + return mode; +} + +static void f_ospi_config_indir_protocol(struct f_ospi *ospi, + const struct spi_mem_op *op) +{ + u8 mode; + u32 prot = 0, val; + int unit; + + /* Set one chip select */ + writel(BIT(ospi->chip_select), ospi->base + OSPI_SSEL); + + mode = f_ospi_get_mode(ospi, op->cmd.buswidth, 1); + prot |= FIELD_PREP(OSPI_PROT_MODE_CODE_MASK, mode); + + mode = f_ospi_get_mode(ospi, op->addr.buswidth, op->addr.nbytes); + prot |= FIELD_PREP(OSPI_PROT_MODE_ADDR_MASK, mode); + + mode = f_ospi_get_mode(ospi, op->data.buswidth, op->data.nbytes); + prot |= FIELD_PREP(OSPI_PROT_MODE_DATA_MASK, mode); + + prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_DATA, OSPI_PROT_SDR); + prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_ALT, OSPI_PROT_SDR); + prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_ADDR, OSPI_PROT_SDR); + prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_CODE, OSPI_PROT_SDR); + + if (ospi->mode & SPI_LSB_FIRST) + prot |= OSPI_PROT_BIT_POS_DATA | OSPI_PROT_BIT_POS_ALT + | OSPI_PROT_BIT_POS_ADDR | OSPI_PROT_BIT_POS_CODE; + + if (ospi->mode & SPI_CPHA) + prot |= OSPI_PROT_SAMP_EDGE; + + /* Examine nbytes % 4 */ + switch (op->data.nbytes & 0x3) { + case 0: + unit = OSPI_PROT_DATA_UNIT_4B; + val = 0; + break; + case 2: + unit = OSPI_PROT_DATA_UNIT_2B; + val = OSPI_DAT_SIZE_EN | (op->data.nbytes - 1); + break; + default: + unit = OSPI_PROT_DATA_UNIT_1B; + val = OSPI_DAT_SIZE_EN | (op->data.nbytes - 1); + break; + } + prot |= FIELD_PREP(OSPI_PROT_DATA_UNIT_MASK, unit); + + switch (op->data.dir) { + case SPI_MEM_DATA_IN: + prot |= OSPI_PROT_DATA_EN; + break; + + case SPI_MEM_DATA_OUT: + prot |= OSPI_PROT_TRANS_DIR_WRITE | OSPI_PROT_DATA_EN; + break; + + case SPI_MEM_NO_DATA: + prot |= OSPI_PROT_TRANS_DIR_WRITE; + break; + + default: + dev_warn(ospi->dev, "Unsupported direction"); + break; + } + + prot |= FIELD_PREP(OSPI_PROT_ADDR_SIZE_MASK, op->addr.nbytes); + prot |= FIELD_PREP(OSPI_PROT_CODE_SIZE_MASK, 1); /* 1byte */ + + writel(prot, ospi->base + OSPI_PROT_CTL_INDIR); + writel(val, ospi->base + OSPI_DAT_SIZE_INDIR); +} + +static int f_ospi_indir_prepare_op(struct f_ospi *ospi, + const struct spi_mem_op *op) +{ + u32 irq_stat_en; + int ret; + + ret = f_ospi_prepare_config(ospi); + if (ret) + return ret; + + f_ospi_config_clk(ospi, ospi->max_speed_hz); + + f_ospi_config_indir_protocol(ospi, op); + + writel(f_ospi_get_dummy_cycle(op), ospi->base + OSPI_DMY_INDIR); + writel(op->addr.val, ospi->base + OSPI_ADDR); + writel(op->cmd.opcode, ospi->base + OSPI_CMD_IDX_INDIR); + + f_ospi_clear_irq(ospi); + + switch (op->data.dir) { + case SPI_MEM_DATA_IN: + irq_stat_en = OSPI_IRQ_READ_BUF_READY | OSPI_IRQ_CS_TRANS_COMP; + break; + + case SPI_MEM_DATA_OUT: + irq_stat_en = OSPI_IRQ_WRITE_BUF_READY | OSPI_IRQ_CS_TRANS_COMP; + break; + + case SPI_MEM_NO_DATA: + irq_stat_en = OSPI_IRQ_CS_TRANS_COMP; + break; + + default: + dev_warn(ospi->dev, "Unsupported direction"); + irq_stat_en = 0; + } + + f_ospi_disable_irq_status(ospi, ~irq_stat_en); + f_ospi_enable_irq_status(ospi, irq_stat_en); + + return f_ospi_unprepare_config(ospi); +} + +static void f_ospi_indir_start_xfer(struct f_ospi *ospi) +{ + /* Write only 1, auto cleared */ + writel(OSPI_TRANS_CTL_START_REQ, ospi->base + OSPI_TRANS_CTL); +} + +static void f_ospi_indir_stop_xfer(struct f_ospi *ospi) +{ + /* Write only 1, auto cleared */ + writel(OSPI_TRANS_CTL_STOP_REQ, ospi->base + OSPI_TRANS_CTL); +} + +static int f_ospi_indir_wait_xfer_complete(struct f_ospi *ospi) +{ + u32 val; + + return readl_poll_timeout(ospi->base + OSPI_IRQ, val, + val & OSPI_IRQ_CS_TRANS_COMP, + OSPI_WAIT_MAX_MSEC); +} + +static int f_ospi_indir_read(struct f_ospi *ospi, + const struct spi_mem_op *op) +{ + u8 *buf = op->data.buf.in; + u32 val; + int i, ret; + + /* E1-2: Prepare transfer operation */ + ret = f_ospi_indir_prepare_op(ospi, op); + if (ret) + goto out; + + f_ospi_indir_start_xfer(ospi); + + /* E3-4: Wait for ready and read data */ + for (i = 0; i < op->data.nbytes; i++) { + ret = readl_poll_timeout(ospi->base + OSPI_IRQ, val, + val & OSPI_IRQ_READ_BUF_READY, + OSPI_WAIT_MAX_MSEC); + if (ret) + goto out; + + buf[i] = readl(ospi->base + OSPI_DAT) & 0xFF; + } + + /* E5-6: Stop transfer if data size is nothing */ + if (!(readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN)) + f_ospi_indir_stop_xfer(ospi); + + /* E7-8: Wait for completion and clear */ + ret = f_ospi_indir_wait_xfer_complete(ospi); + if (ret) + goto out; + + writel(OSPI_IRQ_CS_TRANS_COMP, ospi->base + OSPI_IRQ); + + /* E9: Do nothing if data size is valid */ + if (readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN) + goto out; + + /* E10-11: Reset and check read fifo */ + writel(OSPI_SWRST_INDIR_READ_FIFO, ospi->base + OSPI_SWRST); + + ret = readl_poll_timeout(ospi->base + OSPI_SWRST, val, + !(val & OSPI_SWRST_INDIR_READ_FIFO), + OSPI_WAIT_MAX_MSEC); +out: + return ret; +} + +static int f_ospi_indir_write(struct f_ospi *ospi, + const struct spi_mem_op *op) +{ + u8 *buf = (u8 *)op->data.buf.out; + u32 val; + int i, ret; + + /* F1-3: Prepare transfer operation */ + ret = f_ospi_indir_prepare_op(ospi, op); + if (ret) + goto out; + + f_ospi_indir_start_xfer(ospi); + + if (!(readl(ospi->base + OSPI_PROT_CTL_INDIR) & OSPI_PROT_DATA_EN)) + goto nodata; + + /* F4-5: Wait for buffer ready and write data */ + for (i = 0; i < op->data.nbytes; i++) { + ret = readl_poll_timeout(ospi->base + OSPI_IRQ, val, + val & OSPI_IRQ_WRITE_BUF_READY, + OSPI_WAIT_MAX_MSEC); + if (ret) + goto out; + + writel(buf[i], ospi->base + OSPI_DAT); + } + + /* F6-7: Stop transfer if data size is nothing */ + if (!(readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN)) + f_ospi_indir_stop_xfer(ospi); + +nodata: + /* F8-9: Wait for completion and clear */ + ret = f_ospi_indir_wait_xfer_complete(ospi); + if (ret) + goto out; + + writel(OSPI_IRQ_CS_TRANS_COMP, ospi->base + OSPI_IRQ); +out: + return ret; +} + +static int f_ospi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) +{ + struct f_ospi *ospi = dev_get_priv(slave->dev->parent); + struct dm_spi_slave_plat *slave_plat; + int err = 0; + + slave_plat = dev_get_parent_plat(slave->dev); + ospi->chip_select = slave_plat->cs; + + switch (op->data.dir) { + case SPI_MEM_DATA_IN: + err = f_ospi_indir_read(ospi, op); + break; + + case SPI_MEM_DATA_OUT: + fallthrough; + case SPI_MEM_NO_DATA: + err = f_ospi_indir_write(ospi, op); + break; + + default: + dev_warn(ospi->dev, "Unsupported direction"); + err = -EOPNOTSUPP; + } + + return err; +} + +static bool f_ospi_supports_op_width(const struct spi_mem_op *op) +{ + u8 width_available[] = { 0, 1, 2, 4, 8 }; + u8 width_op[] = { op->cmd.buswidth, op->addr.buswidth, + op->dummy.buswidth, op->data.buswidth }; + bool is_match_found; + int i, j; + + for (i = 0; i < ARRAY_SIZE(width_op); i++) { + is_match_found = false; + + for (j = 0; j < ARRAY_SIZE(width_available); j++) { + if (width_op[i] == width_available[j]) { + is_match_found = true; + break; + } + } + + if (!is_match_found) + return false; + } + + return true; +} + +static bool f_ospi_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + if (f_ospi_get_dummy_cycle(op) > OSPI_DUMMY_CYCLE_MAX) + return false; + + if (op->addr.nbytes > 4) + return false; + + if (!f_ospi_supports_op_width(op)) + return false; + + return true; +} + +static int f_ospi_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op) +{ + op->data.nbytes = min((int)op->data.nbytes, (int)(OSPI_DAT_SIZE_MAX)); + + return 0; +} + +static const struct spi_controller_mem_ops f_ospi_mem_ops = { + .adjust_op_size = f_ospi_adjust_op_size, + .supports_op = f_ospi_supports_op, + .exec_op = f_ospi_exec_op, +}; + +static int f_ospi_set_speed(struct udevice *bus, u32 speed) +{ + struct f_ospi *ospi = dev_get_priv(bus); + + ospi->max_speed_hz = speed; + + return 0; +} + +static int f_ospi_set_mode(struct udevice *bus, u32 mode) +{ + struct f_ospi *ospi = dev_get_priv(bus); + + ospi->mode = mode; + + return 0; +} + +static int f_ospi_init(struct f_ospi *ospi) +{ + int ret; + + ret = f_ospi_prepare_config(ospi); + if (ret) + return ret; + + /* Disable boot signal */ + writel(OSPI_ACC_MODE_BOOT_DISABLE, ospi->base + OSPI_ACC_MODE); + + f_ospi_config_dll(ospi); + + /* Disable IRQ */ + f_ospi_clear_irq(ospi); + f_ospi_disable_irq_status(ospi, OSPI_IRQ_ALL); + f_ospi_disable_irq_output(ospi, OSPI_IRQ_ALL); + + return f_ospi_unprepare_config(ospi); +} + +static int f_ospi_of_to_plat(struct udevice *dev) +{ + struct f_ospi *ospi = dev_get_priv(dev); + + ospi->base = dev_read_addr_ptr(dev); + ospi->num_cs = dev_read_u32_default(dev, "num-cs", OSPI_NUM_CS); + + return 0; +} + +static int f_ospi_probe(struct udevice *dev) +{ + struct f_ospi *ospi = dev_get_priv(dev); + int ret; + + ospi->dev = dev; + + ret = clk_get_by_index(dev, 0, &ospi->clk); + if (ret < 0) { + dev_err(dev, "Failed to get clock\n"); + goto err_put_ctlr; + } + + ret = clk_enable(&ospi->clk); + if (ret) { + dev_err(dev, "Failed to enable the clock\n"); + goto err_put_ctlr; + } + + ret = f_ospi_init(ospi); + if (ret) + goto err_disable_clk; + + return 0; + +err_disable_clk: + clk_disable(&ospi->clk); + +err_put_ctlr: + dev_err(dev, "Socionext F_OSPI probe failed\n"); + return ret; +} + +static int f_ospi_remove(struct udevice *dev) +{ + struct f_ospi *ospi = dev_get_priv(dev); + + clk_disable(&ospi->clk); + + return 0; +} + +static const struct dm_spi_ops f_ospi_ops = { + .set_speed = f_ospi_set_speed, + .set_mode = f_ospi_set_mode, + .mem_ops = &f_ospi_mem_ops, +}; + +static const struct udevice_id f_ospi_dt_ids[] = { + { .compatible = "socionext,f-ospi" }, + {} +}; + +U_BOOT_DRIVER(f_ospi) = { + .name = "sn-f-ospi", + .id = UCLASS_SPI, + .of_match = f_ospi_dt_ids, + .of_to_plat = f_ospi_of_to_plat, + .ops = &f_ospi_ops, + .probe = f_ospi_probe, + .remove = f_ospi_remove, + .priv_auto = sizeof(struct f_ospi), +}; |