diff options
author | Simon Glass <sjg@chromium.org> | 2019-02-17 06:24:49 +0300 |
---|---|---|
committer | Bin Meng <bmeng.cn@gmail.com> | 2019-02-20 10:25:30 +0300 |
commit | c882163b09b8a2c52e3dd8acd7d296d6d06d1f2e (patch) | |
tree | 11000150b6e532a79124e845948330992fb76a24 /drivers | |
parent | 2cd2bc20c4db41d34e735c29b63a9c0b01f8039e (diff) | |
download | u-boot-c882163b09b8a2c52e3dd8acd7d296d6d06d1f2e.tar.xz |
x86: sandbox: pch: Add a CONFIG option for PCH
At present this uclass is selected only on x86. In order to add a test for
it, it must also support sandbox. Create a new CONFIG_PCH option and
enable it on x86 and sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/Kconfig | 2 | ||||
-rw-r--r-- | drivers/Makefile | 3 | ||||
-rw-r--r-- | drivers/pch/Kconfig | 9 |
3 files changed, 13 insertions, 1 deletions
diff --git a/drivers/Kconfig b/drivers/Kconfig index e9fbadd13d..f24351ac4f 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -64,6 +64,8 @@ source "drivers/nvme/Kconfig" source "drivers/pci/Kconfig" +source "drivers/pch/Kconfig" + source "drivers/pcmcia/Kconfig" source "drivers/phy/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index eca023ac04..a7bba3ed56 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -86,7 +86,8 @@ obj-y += misc/ obj-$(CONFIG_MMC) += mmc/ obj-$(CONFIG_NVME) += nvme/ obj-y += pcmcia/ -obj-$(CONFIG_X86) += pch/ +obj-y += dfu/ +obj-$(CONFIG_PCH) += pch/ obj-y += phy/allwinner/ obj-y += phy/marvell/ obj-y += rtc/ diff --git a/drivers/pch/Kconfig b/drivers/pch/Kconfig new file mode 100644 index 0000000000..18f006de24 --- /dev/null +++ b/drivers/pch/Kconfig @@ -0,0 +1,9 @@ +config PCH + bool "Enable Platform-controller Hub (PCH) support" + depends on X86 || SANDBOX + help + Most x86 chips include a PCH which is responsible for handling + parts of the system not handled by that CPU. It supersedes the + northbridge / southbridge architecture that was previously used. The + PCH allows for higher performance since the memory functions are + handled in the CPU. |