diff options
| author | Chris Packham <judge.packham@gmail.com> | 2018-06-03 07:21:26 +0300 |
|---|---|---|
| committer | Joe Hershberger <joe.hershberger@ni.com> | 2018-06-13 21:54:17 +0300 |
| commit | 3cb51dad0dff5de5f4fff25639d2a88efead0691 (patch) | |
| tree | c84a5d47d2f376e16252c1c685f908b69a96f9bc /drivers | |
| parent | 199b27bb70e72819782095cd3364a2245137c3eb (diff) | |
| download | u-boot-3cb51dad0dff5de5f4fff25639d2a88efead0691.tar.xz | |
net: phy: mv88e61xx: Force CPU port link up
When connecting to from a CPU direct to a 88e6097 typically RGMII is
used. In order for traffic to actually pass we need to force the link up
so the CPU MAC on the other end will see the link.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/phy/mv88e61xx.c | 51 |
1 files changed, 30 insertions, 21 deletions
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 17040bd6cc..ea54a15310 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -705,6 +705,31 @@ unforce: return res; } +static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) +{ + int val; + + val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); + if (val < 0) + return val; + + val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK | + PORT_REG_PHYS_CTRL_FC_VALUE); + val |= PORT_REG_PHYS_CTRL_PCS_AN_EN | + PORT_REG_PHYS_CTRL_PCS_AN_RST | + PORT_REG_PHYS_CTRL_FC_FORCE | + PORT_REG_PHYS_CTRL_DUPLEX_VALUE | + PORT_REG_PHYS_CTRL_DUPLEX_FORCE | + PORT_REG_PHYS_CTRL_SPD1000; + + if (port == CONFIG_MV88E61XX_CPU_PORT) + val |= PORT_REG_PHYS_CTRL_LINK_VALUE | + PORT_REG_PHYS_CTRL_LINK_FORCE; + + return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, + val); +} + static int mv88e61xx_set_cpu_port(struct phy_device *phydev) { int val; @@ -748,6 +773,11 @@ static int mv88e61xx_set_cpu_port(struct phy_device *phydev) if (val < 0) return val; } + } else { + val = mv88e61xx_fixed_port_setup(phydev, + CONFIG_MV88E61XX_CPU_PORT); + if (val < 0) + return val; } return 0; @@ -810,27 +840,6 @@ static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy) return 0; } -static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) -{ - int val; - - val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); - if (val < 0) - return val; - - val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK | - PORT_REG_PHYS_CTRL_FC_VALUE); - val |= PORT_REG_PHYS_CTRL_PCS_AN_EN | - PORT_REG_PHYS_CTRL_PCS_AN_RST | - PORT_REG_PHYS_CTRL_FC_FORCE | - PORT_REG_PHYS_CTRL_DUPLEX_VALUE | - PORT_REG_PHYS_CTRL_DUPLEX_FORCE | - PORT_REG_PHYS_CTRL_SPD1000; - - return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, - val); -} - static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy) { int val; |